A Board Level Parallel Test Circuit and a Short Circuit Failure Repair Circuit for High-Density, Low-Power DRAMs (Special Issue on Circuit Technologies for Memory and Analog LSIs)
スポンサーリンク
概要
- 論文の詳細を見る
This paper proposes a new test mode circuit which enables the massively parallel test of DRAMs with a standard LSI tester with little chip area penalty. It is useful to enhance the test throughput that can't be improved by the conventional multi-bit test mode. And a new redundancy circuit that detects and repairs the short circuit failures in the memory cell array is also proposed. It greatly improves the yield of super low power 256Mbit DRAMs.
- 社団法人電子情報通信学会の論文
- 1997-04-25
著者
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OZAKI Hideyuki
Renesas Technology Corp.
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YAMADA Michihiro
ULSI Development Center, Mitsubishi Electric Corporation
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HIDAKA Hideto
ULSI Laboratory, Mitsubishi Electric Corporation
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Ozaki H
Renesas Technology Corp.
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OZAKI Hideyuki
ULSI Development Center, Mitsubishi Electric Corp.
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Ozaki Hideyuki
Ulsi Laboratory Mitsubishi Electric Corporation
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FURUTANI Kiyohiro
ULSI Laboratory, Mitsubishi Electric Corporation
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OOISHI Tsukasa
ULSI Laboratory, Mitsubishi Electric Corporation
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ASAKURA Mikio
ULSI Laboratory, Mitsubishi Electric Corporation
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Hidaka H
Yrp Mobil Telecommunications Key Technol. Res. Lab. Co. Ltd. Yokosuka‐shi Jpn
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Hidaka Hideto
Ulsi Laboratory Mitsubishi Electric Corporation
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Asakura Mikio
Ulsi Laboratory Mitsubishi Electric Corporation
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Ooishi T
Ulsi Laboratory Mitsubishi Electric Corporation
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Oashi Toshiyuki
Ulsi Development Center Mitsubishi Electric Corporation
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Ooishi Tsukasa
Ulsi Laboratory Mitsubishi Electric Corporation
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Furutani K
Renesas Technol. Corp. Itami‐shi Jpn
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Yamada Michihiro
Ulsi Laboratory Mitsubishi Electric Corporation
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Yamada Michihiro
Ulsi Development Center Mitsubishi Electric Corporation
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