A Line-Mode Test with Data Register for ULSI Memory Architecture (Special Issue on LSI Memories)
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概要
- 論文の詳細を見る
We propose an advanced hyper parallel testing method which improves the line-mode test method by adding data inversion registers which we call the Advanced Line-mode Test (ALT). This testing method has the same testing capability as the conventional bit-by-bit and multi-bit test method (MBT), because it enables the application of a high sensitive and practical test patterns under the hyper parallel condition. The testing time for fixed data patterns are reduced by 1 / 1900 (all-0 / 1, checker board, and etc.). Moreover, the ALT can be applicable to the continuous patterns (march, walking, and etc.). The ALT improved from the line-mode test with registers and comparators (LTR) is able to applicable to the most test patterns and to reduce the testing time remarkably, and is suitable for the ULSI memories.
- 社団法人電子情報通信学会の論文
- 1993-11-25
著者
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Matsuda Yoshio
System Lsi Laboratory Mitsubishi Electric Corporation
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FUJISHIMA Kazuyasu
ULSI Development Center, Mitsubishi Electric Corp.
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OOISHI Tsukasa
ULSI Laboratory, Mitsubishi Electric Corporation
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Tsukude Masaki
Ulsi Laboratory Mitsubishi Electric Corporation
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Ooishi Tsukasa
Ulsi Laboratory Mitsubishi Electric Corporation
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Fujishima Kazuyasu
Ulsi Development Center Mitsubishi Electric Corp.
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Fujishima Kazuyasu
Ulsi Laboratory Mitsubishi Electric Corporation
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Arimoto Kazutani
ULSI Laboratory, Mitsubishi Electric Corporation
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Arimoto Kazutani
Ulsi Laboratory Mitsubishi Electric Corporation
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Matsuda Yoshio
System-lsi Laboratory Mitsubishi Electric Corporation
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Matsuda Yoshio
System Lsi Development Center Mitsubishi Electric Corporation
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