A Blanket Source Line Architecture with Triple Metal for Giga Scale Memory LSIs (Special Issue on ULSI Memory Technology)
スポンサーリンク
概要
- 論文の詳細を見る
A new source line routing architecture features a blanket-like source line made of double aluminum layers by utilizlng a pure tungsten metal layer as the local interconnection layer in the peripheral region. The relaxed pitch of the signal lines improves the RC time delay constant of the signal lines and gives stable V_<cc> and V_<ss> levels throughout the chip. Furthermore, this architecture brings about an 8% area reduction of the peripheral region in 256 Mb DRAMs with high performance, when used in collaboration with hierarchical bit-line architecture.
- 社団法人電子情報通信学会の論文
- 1996-06-25
著者
-
Tsukude M
Ulsi Laboratory Mitsubishi Electric Corporation
-
Tsukude Masaki
Ulsi Laboratory Mitsubishi Electric Corporation
-
Yamagata T
Mitsubishi Electric Corp. Itami‐shi Jpn
-
Yamagata Tadato
Ulsi Laboratory Mitsubishi Electric Corporation
-
Arimoto Kazutami
Ulsi Laboratory Mitsubishi Electric Corporation
-
Arimoto Kazutami
Ulsi Development Center Mitsubishi Electric Corporation
-
Tomishima S
Ulsi Laboratory Mitsubishi Electric Corporation
-
Tomishima Shigeki
Ulsi Laboratory Mitsubishi Electric Corporation
-
KUGE Shigehiro
the ULSI Laboratory, Mitsubishi Electric Corporation
-
KUGE Shigehiro
ULSI Laboratory, Mistubishi Electric Corporation
-
Kuge Shigehiro
The Ulsi Laboratory Mitsubishi Electric Corporation
関連論文
- Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM (Special Issue on Ultra-High-Speed IC and LSI Technology)
- Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's (Special Issue on ULSI Memory Technology)
- A 0.18 ★m 32 Mb Embedded DRAM Macro for 3-D Graphics Controller
- A Line-Mode Test with Data Register for ULSI Memory Architecture (Special Issue on LSI Memories)
- A Flexible Search Managing Circuitry for High-Density Dynamic CAMs (Speial Section on High Speed and High Density Multi Functional LSI Memories)
- A Bitline Control Circuit Scheme and Redundancy Technique for High-Density Dynamic Content Addressable Memories (Special Issue on LSI Memories)
- Electronic Band Structures for Non-Magnetic and Ferromagnetic States of Transition-Metal Intercalation Compound Mn_TaS_2
- A Well-Synchronized Sensing/Equalizing Method for Sub-1.0-V Operating Advanced DRAM's (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
- A Smart Design Methodology with Distributed Extra Gate-Arrays for Advanced ULSI Memories (Special Issue on LSI Memories)
- Large Scale Embedded DRAM Technology(Special Issue on Multimedia, Network, and DRAM LSIs)
- A Single Chip Multiprocessor Integrated with High Density DRAM
- A Long Data Retention SOI DRAM with the Body Refresh Function (Special Issue on New Concept Device and Novel Architecture LSIs)
- SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories
- A Blanket Source Line Architecture with Triple Metal for Giga Scale Memory LSIs (Special Issue on ULSI Memory Technology)
- Circuit Technology for Giga-bit/Low Voltage Operating SOI-DRAM (Special Issue on SOI Devices and Their Process Technologies)