Large Scale Embedded DRAM Technology(Special Issue on Multimedia, Network, and DRAM LSIs)

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概要

• 論文の詳細を見る

• The features for the integration of lTr/lC DRAM and logic for graphic and multimedia applications are surveyed. The key circuit/process technology for large scale embedded DRAM cores is described. The methods to improve transistor performance and gate density are shown. Noise immunity design and easy customization techniques are also introduced.

• 社団法人電子情報通信学会の論文
• 1998-05-25

著者

• YAMAZAKI Akira

  ULSI Development Center, Mitsubishi Electric Corp.

• Yamagata Tadato

  Ulsi Laboratory Mitsubishi Electric Corporation

• TANIGUCHI Makoto

  Planning & Marketing Administration Dept., Mitsubishi Electric Corporation

• Yamada Michihiro

  Ulsi Laboratory Mitsubishi Electric Corporation

• Yamada Michihiro

  Ulsi Development Center Mitsubishi Electric Corporation

• Arita Yutaka

  Ulsi Laboratory Mitsubishi Electric Corporation

• Taniguchi Makoto

  Planning & Marketing Administration Dept. Mitsubishi Electric Corporation

• Yamazaki Akira

  Ulsi Laboratory Mitsubishi Electric Corporation

関連論文

• Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM (Special Issue on Ultra-High-Speed IC and LSI Technology)
• A 0.18 ★m 32 Mb Embedded DRAM Macro for 3-D Graphics Controller
• A Board Level Parallel Test Circuit and a Short Circuit Failure Repair Circuit for High-Density, Low-Power DRAMs (Special Issue on Circuit Technologies for Memory and Analog LSIs)
• A Bitline Control Circuit Scheme and Redundancy Technique for High-Density Dynamic Content Addressable Memories (Special Issue on LSI Memories)
• Interface Technologies for Memories and ASICs : Review and Future Direction (Special Issue on Ultra-High-Speed IC and LSI Technology)
• 111-MHz 1-Mbit CMOS Synchronous Burst SRAM Using a Clock Activation Control Method (Special Issue on ULSI Memory Technology)
• A 5.8 ns 256 kb SRAM with 0.4μm Super-CMOS Process Technology (Special Issue on Circuit Technologies for Memory and Analog LSIs)
• A 4-Mb SRAM Using a New Hierarchical Bit Line Organization Utilizing a T-Shaped Bit Line for a Small Sized Die (Special Issue on ULSI Memory Technology)
• Large Scale Embedded DRAM Technology(Special Issue on Multimedia, Network, and DRAM LSIs)
• A Long Data Retention SOI DRAM with the Body Refresh Function (Special Issue on New Concept Device and Novel Architecture LSIs)
• A Blanket Source Line Architecture with Triple Metal for Giga Scale Memory LSIs (Special Issue on ULSI Memory Technology)

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