A 5.8 ns 256 kb SRAM with 0.4μm Super-CMOS Process Technology (Special Issue on Circuit Technologies for Memory and Analog LSIs)
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概要
- 論文の詳細を見る
This paper presents Super-CMOS SRAM process technology that integrates bipolar and CMOS transistors in a chip while adding only one ion implantation step and no lithography mask steps to the conventional CMOS SRAM process. The Super-CMOS SRAM process therefore has the same process cost as the CMOS SRAMs, while it achieves higher access speeds. In order to demonstrate the Super-CMOS SRAM, we have developed a 3.3V/5V 256kb SRAM using 0.4μm Super-CMOS process technology. By applying bipolar transistors to the sense amplifier circuits, a high-speed access time of 5.8ns with a 3.0V power supply is successfully achieved.
- 社団法人電子情報通信学会の論文
- 1997-04-25
著者
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YAMADA Michihiro
ULSI Development Center, Mitsubishi Electric Corporation
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Wada Tomohisa
ULSI Laboratory, Mitsubishi Electric Corporation
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Arita Y
Mitsubishi Electric Corp. Itami‐shi Jpn
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Wada Tomohisa
Ulsi Laboratory Mitsubishi Electric Corporation
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KOZARU Kunihiko
ULSI Laboratory, Mitsubishi Electric Corporation
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KINOSHITA Atsushi
Memory IC Division, Mitsubishi Electric Corporation
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ARITA Yutaka
ULSI Laboratory, Mitsubishi Electric Corporation
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Yamada Michihiro
Ulsi Laboratory Mitsubishi Electric Corporation
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Yamada Michihiro
Ulsi Development Center Mitsubishi Electric Corporation
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Arita Yutaka
Ulsi Laboratory Mitsubishi Electric Corporation
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Kozaru Kunihiko
Ulsi Laboratory Mitsubishi Electric Corporation
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Kinoshita Atsushi
Memory Ic Division Mitsubishi Electric Corporation
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