111-MHz 1-Mbit CMOS Synchronous Burst SRAM Using a Clock Activation Control Method (Special Issue on ULSI Memory Technology)

概要

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This paper reports a 32 k × 32 1-Mbit CMOS synchronous pipelined burst SRAM. A clock access time of 3.6 ns and a minimum cycle time of 9 ns (111 MHz operation) were obtained. An active current of 210 mA at 111 MHz and a standby current of 2 μA were successfully realized. These results can be obtained by a new activation control method in which the internal clock pulses control the decoders, the low resistive bit line and memory cell GND line and the optimization of write recovery timing and data sense timing.
社団法人電子情報通信学会の論文
1996-06-25