A Hierarchical Global Router for Macro-Block-Embedded Sea-of-Gates (Special Section on VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
A fast and efficient heuristic hierarchical global router for Sea-of-Gates (SOG) with embedded macro-blocks is described. The key point in the method is to carry out a new optimal domain decomposition scheduling at every hierarchical level. This scheduling is intended to avoid macro-block-through wirings and to reduce wiring congestion near macro-blocks which may occur at lower levels. The new global router yielded superior results compared with previous hierarchical routers and a non-hierarchical maze router by evaluating with several actual SOG circuits including a 300K gate master chip and benchmark data supplied from MCNC. Overflows were reduced to one-half or one-quarter for macro-block embedded data compared with previous hierarchical routers. Concerning the running time, the router remarkably outperformed the non-hierarchical maze router, which took more than 390 times longer time for the tested large data.
- 社団法人電子情報通信学会の論文
- 1993-10-25
著者
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Goto N
Ulsi Research Labolatories R & D Center Toshiba Corporation
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Yamada M
Mitsubishi Electric Corp. Itami‐shi Jpn
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Kuribayashi Mototaka
the Semiconductor Device Engineering Laboratory, TOSHIBA CORPORATION
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Yamada Masaaki
the Research & Development Center, TOSHIBA CORPORATION
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Mitsuhashi Takashi
the Research & Development Center, TOSHIBA CORPORATION
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Goto Nobuyuki
the Research & Development Center, TOSHIBA CORPORATION
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Yamada M
Kanazawa Univ. Kanazawa‐shi Jpn
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Mitsuhashi Takashi
Semiconductor Da & Test Center Toshiba Corporation
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Kuribayashi Mototaka
The Semiconductor Device Engineering Laboratory Toshiba Corporation
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