Synergistic Power/Area Optimization with Transistor Sizing and Wire Length Minimization
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概要
- 論文の詳細を見る
The paper proposes a method to synthesize low-power control-logic modules by combining transistor-size optimization and transistor layout. Transistor sizing and layout work synergistically to achieve power/area optimization. Transistor size minimization provides more spaces for layout to be compacted. Layout compaction results in shorter wire length (i.e. smaller load capacitance), which allows transistors to become smaller. The details of transistor sizing and layout compaction are also described. When applied to circuits with up to 10,000 transistors, the optimizer reduced the average transistor size to one eighth while maintaining the same delay. The power dissipation is cut to half even when wiring capacitances are dominant.
- 社団法人電子情報通信学会の論文
- 1995-04-25
著者
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Goto N
Ulsi Research Labolatories R & D Center Toshiba Corporation
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Yamada M
Mitsubishi Electric Corp. Itami‐shi Jpn
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GOTO Nobuyuki
ULSI Research Labolatories, R & D Center, TOSHIBA CORPORATION
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Yamada Masaaki
ULSI Research Labs., RampD Center, TOSHIBA CORPORATION
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Kurosawa Sachiko
ULSI Research Labs., RampD Center, TOSHIBA CORPORATION
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Nojima Reiko
ULSI Research Labs., RampD Center, TOSHIBA CORPORATION
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Kojima Naohito
ULSI Research Labs., RampD Center, TOSHIBA CORPORATION
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Mitsuhashi Takashi
ULSI Research Labs., RampD Center, TOSHIBA CORPORATION
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Nojima Reiko
Semiconductor Da & Test Center Toshiba Corporation
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Kojima Naohito
Semiconductor Da & Test Center Toshiba Corporation
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Yamada M
Kanazawa Univ. Kanazawa‐shi Jpn
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Kurosawa Sachiko
Semiconductor Da & Test Center Toshiba Corporation
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Mitsuhashi Takashi
Semiconductor Da & Test Center Toshiba Corporation
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