Power and Area Minimization by Reorganizing CMOS Complex-Gates (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)

概要

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This paper proposes a method for achieving low-power control-logic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor layout. Complex gate reorganization minimizes transistor count and net count without changing the functionality of the circuit. Transistor sizing and layout are interdependent, the optimization of one results in the optimization of the other. The authors applied the reorganization method to a 10,846-transistor circuit, and succeeded in reducing the transistor count by 10%, and the net count by 9%. Transistor sizing and layout compaction reduced the average transistor size by one tenth, while the same delay was maintained. Total circuit capacitance, which is strongly related to power dissipation, was cut to 36%, even when wiring capacitances were dominant.
社団法人電子情報通信学会の論文
1996-03-25