Delay and Skew Minimized Clock Tree Synthesis for Embedded Arrays (Special Issue on Synthesis and Verification of Hardware Design)

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概要

• 論文の詳細を見る

• This paper presents a novel clock routing method used in constructing an optimal clock tree for embedded array chips by determining the route so as to minimize both delay and skew. The proposed method features constructing a tree by optimal node-pair merging, predicting the upper side balanced-tree structure, based on accurate global path or delay estimation. By this method, in the case of the chip with large macro cells, the delay estimation error has been within 10%.

• 社団法人電子情報通信学会の論文
• 1996-10-25

著者

• KOJIMA Naohito

  Semiconductor DA & Test Center, TOSHIBA CORPORATION

• Kojima Naohito

  Semiconductor Da Amp Test Engineering Center Toshiba Corporation

• Minami Fumihiro

  Semiconductor Da Amp Test Engineering Center Toshiba Corporation

• Takano Midori

  Semiconductor Da Amp Test Engineering Center Toshiba Corporation

関連論文

• Power and Area Minimization by Reorganizing CMOS Complex-Gates (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
• Gate Delay Estimation in STA under Dynamic Power Supply Noise
• Delay and Skew Minimized Clock Tree Synthesis for Embedded Arrays (Special Issue on Synthesis and Verification of Hardware Design)

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