YAMADA Michihiro | ULSI Development Center, Mitsubishi Electric Corporation

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著作論文

Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM (Special Issue on Ultra-High-Speed IC and LSI Technology)
A Board Level Parallel Test Circuit and a Short Circuit Failure Repair Circuit for High-Density, Low-Power DRAMs (Special Issue on Circuit Technologies for Memory and Analog LSIs)
111-MHz 1-Mbit CMOS Synchronous Burst SRAM Using a Clock Activation Control Method (Special Issue on ULSI Memory Technology)
A 5.8 ns 256 kb SRAM with 0.4μm Super-CMOS Process Technology (Special Issue on Circuit Technologies for Memory and Analog LSIs)
A 4-Mb SRAM Using a New Hierarchical Bit Line Organization Utilizing a T-Shaped Bit Line for a Small Sized Die (Special Issue on ULSI Memory Technology)

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