Circuit Technology for Giga-bit/Low Voltage Operating SOI-DRAM (Special Issue on SOI Devices and Their Process Technologies)
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概要
- 論文の詳細を見る
The key circuit technologies for future giga-bit/low voltage operating high performance SOI-DRAM is described. Emphasis is made especially on the considerations for ways to overcome floating-body effects in order to obtain very long static/dynamic data retention time. A new scheme called a super body synchronous sensing scheme is proposed for low voltage operation at 1V.
- 社団法人電子情報通信学会の論文
- 1997-03-25
著者
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Yasuoka Akihiko
Ulsi Laboratory Mitsubishi Electric Corporation
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Arimoto Kazutami
Ulsi Laboratory Mitsubishi Electric Corporation
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Arimoto Kazutami
Ulsi Development Center Mitsubishi Electric Corporation
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