SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories
スポンサーリンク
概要
- 論文の詳細を見る
- 1996-07-25
著者
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MORISHITA Fukashi
Renesas Technology Corp.
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Tsukude M
Ulsi Laboratory Mitsubishi Electric Corporation
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Yamagata T
Mitsubishi Electric Corp. Itami‐shi Jpn
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Arimoto Kazutami
System Core Technology Div. Renesas Technology Corp.
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Arimoto Kazutami
Ulsi Laboratory Mitsubishi Electric Corporation
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Tsuruda Takahiro
The Ulsi Laboratory Mitsubishi Electric Corporation
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Morishita Fukashi
System Core Technology Div. Renesas Technology Corp.
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Tomishima S
Ulsi Laboratory Mitsubishi Electric Corporation
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KUGE Shigehiro
the ULSI Laboratory, Mitsubishi Electric Corporation
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MORISHITA Fukashi
the ULSI Laboratory, Mitsubishi Electric Corporation
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TOMISHIMA Shigeki
the ULSI Laboratory, Mitsubishi Electric Corporation
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TSUKUDE Masaki
the ULSI Laboratory, Mitsubishi Electric Corporation
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YAMAGATA Tadako
the ULSI Laboratory, Mitsubishi Electric Corporation
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ARIMOTO Kazutami
the ULSI Laboratory, Mitsubishi Electric Corporation
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Kuge Shigehiro
The Ulsi Laboratory Mitsubishi Electric Corporation
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Morishita Fukashi
Renesas Technology Corporation
関連論文
- A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros(Integrated Electronics)
- A Low Power Embedded DRAM Macro for Battery-Operated LSIs(Power Optimization)(VLSI Design and CAD Algorithms)
- Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM (Special Issue on Ultra-High-Speed IC and LSI Technology)
- Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's (Special Issue on ULSI Memory Technology)
- Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor(Image Processing and Video Processing)
- A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test
- An Embedded DRAM Hybrid Macro with Auto Signa Management and Enhanced-on-Chip Tester
- A 0.18 ★m 32 Mb Embedded DRAM Macro for 3-D Graphics Controller
- A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform(Next-Generation Memory for SoC,VLSI Technology toward Frontiers of New Market)
- A Flexible Search Managing Circuitry for High-Density Dynamic CAMs (Speial Section on High Speed and High Density Multi Functional LSI Memories)
- A Bitline Control Circuit Scheme and Redundancy Technique for High-Density Dynamic Content Addressable Memories (Special Issue on LSI Memories)
- Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor
- Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer(Image Processing and Video Processing)
- A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC(Novel Device Architectures and System Integration Technologies)
- A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features(Integrated Electronics)
- Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh(Memory, Low-Power LSI and Low-Power IP)
- On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform
- A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI(Memory,Low-Power, High-Speed LSIs and Related Technologies)
- An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design(Novel Device Architectures and System Integration Technologies)
- Accomplishment of At-Speed BISR for Embedded DRAMs(Special Issue on Test and Verification of VLSI)
- Electronic Band Structures for Non-Magnetic and Ferromagnetic States of Transition-Metal Intercalation Compound Mn_TaS_2
- Dynamic Floating Body Control SOI CMOS for Power Managed Multimedia ULSIs
- A Well-Synchronized Sensing/Equalizing Method for Sub-1.0-V Operating Advanced DRAM's (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
- A Long Data Retention SOI DRAM with the Body Refresh Function (Special Issue on New Concept Device and Novel Architecture LSIs)
- SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories
- A Blanket Source Line Architecture with Triple Metal for Giga Scale Memory LSIs (Special Issue on ULSI Memory Technology)
- Circuit Technology for Giga-bit/Low Voltage Operating SOI-DRAM (Special Issue on SOI Devices and Their Process Technologies)