A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform(Next-Generation Memory for SoC,<Special Section>VLSI Technology toward Frontiers of New Market)
スポンサーリンク
概要
- 論文の詳細を見る
The advanced-DFM (Design For Manufacturability) RAM provides the solution for the limitation of SRAM voltage scaling down and the countermeasure of the process fluctuations. The characteristics of this RAM are the voltage scalability (@0.6V operation) with wide operating margin and the reliability of long data retention time. The memory cell consists of 2 Cell/bit with the complementary dynamic memory operation and has the 1 Cell/bit test mode for the accelerated screening against the marginal cells. The GND bitline pre-charge sensing scheme and SSW (Sense Synchronized Write) peripheral circuit technologies are also adopted for the low voltage and DFV (Dynamic Frequency and Voltage) controllable SoC which will be strongly required from the many kinds of applications. This RAM supports the DFM functions with both good cell/bit for advanced process technologies and the voltage scalable SoC memory platform.
- 2007-10-01
著者
-
MORISHITA Fukashi
Renesas Technology Corp.
-
Dosaka K
System Core Technology Div. System Solution Business Group Renesas Technology Co.
-
Dosaka Katsumi
System Core Technology Div. Renesas Technology Corp.
-
ARIMOTO Kazutami
System Core Technology Div. System Solution Business Group, Renesas Technology Co.
-
SHIMANO Hiroki
System Core Technology Div., Renesas Technology Corp.
-
MORISHITA Fukashi
System Core Technology Div., Renesas Technology Corp.
-
Shimano Hiroki
System Core Technology Div. Renesas Technology Corp.
-
Arimoto Kazutami
System Core Technology Div. Renesas Technology Corp.
-
Morishita Fukashi
System Core Technology Div. Renesas Technology Corp.
-
Morishita Fukashi
Renesas Technology Corporation
関連論文
- A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros(Integrated Electronics)
- A Low Power Embedded DRAM Macro for Battery-Operated LSIs(Power Optimization)(VLSI Design and CAD Algorithms)
- Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM (Special Issue on Ultra-High-Speed IC and LSI Technology)
- Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's (Special Issue on ULSI Memory Technology)
- Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor(Image Processing and Video Processing)
- A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test
- An Embedded DRAM Hybrid Macro with Auto Signa Management and Enhanced-on-Chip Tester
- A 0.18 ★m 32 Mb Embedded DRAM Macro for 3-D Graphics Controller
- A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform(Next-Generation Memory for SoC,VLSI Technology toward Frontiers of New Market)
- Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor
- Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer(Image Processing and Video Processing)
- A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC(Novel Device Architectures and System Integration Technologies)
- A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features(Integrated Electronics)
- Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh(Memory, Low-Power LSI and Low-Power IP)
- On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform
- A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI(Memory,Low-Power, High-Speed LSIs and Related Technologies)
- An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design(Novel Device Architectures and System Integration Technologies)
- Accomplishment of At-Speed BISR for Embedded DRAMs(Special Issue on Test and Verification of VLSI)
- Dynamic Floating Body Control SOI CMOS for Power Managed Multimedia ULSIs
- A Well-Synchronized Sensing/Equalizing Method for Sub-1.0-V Operating Advanced DRAM's (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
- A Long Data Retention SOI DRAM with the Body Refresh Function (Special Issue on New Concept Device and Novel Architecture LSIs)
- SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories