A Low Power Embedded DRAM Macro for Battery-Operated LSIs(Power Optimization)(<Special Section>VLSI Design and CAD Algorithms)

概要

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low power 16Mb embedded DRAM (eDRAM) macro is fabricated using 0.15 μm logic -based embedded DRAM process technology. A 0.5 μm^2 CUB (c__-apacitor u__-nder b__-it-line) DRAM cell is newly developed for this process. Novel start-up and dynamic fuse-data loading circuit are developed to realize easy customization of memory capacities with minimum area penalty. A new write-mask control circuit using write-gate sense-amplifier is adopted in order to apply column shift-redundancy circuit. Various low power technologies including unique "non-precharge read-data bus" method are applied. In the test-chip adopting new process-technology and three original circuit-design techniques, random column operation of 166 MHz and data retention power of 123μW are demonstrated at 1.5V power supply.
社団法人電子情報通信学会の論文
2003-12-01