A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC(<Special Section>Novel Device Architectures and System Integration Technologies)

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概要

• 論文の詳細を見る

• This paper describes a novel TCAM architecture designed for enhancing the soft-error immunity. An associated embedded DRAM and ECC circuits are placed next to TCAM macro to implement a unique methodology of recovering upset bits due to soft errors. The proposed configuration allows an improvement of soft-error immunity by 6 orders of magnitude compared with the conventional TCAM. We also propose a novel testing methodology of the soft-error rate with a fast parallel multi-bit test. In addition, the proposed architecture resolves the critical problem of the look-up table maintenance of TCAM. The design techniques reported in this paper are especially attractive for realizing soft-error immune, high-performance TCAM chips.

• 社団法人電子情報通信学会の論文
• 2006-11-01

著者

• ARIMOTO Kazutami

  Renesas Technology

• MORISHITA Fukashi

  Renesas Technology Corp.

• NODA Hideyuki

  Renesas Technology Corp.

• DOSAKA Katsumi

  Renesas Technology Corp.

• Noda H

  System Core Technology Div. System Solution Business Group Renesas Technology Co.

• Dosaka K

  System Core Technology Div. System Solution Business Group Renesas Technology Co.

• Mattausch Hans

  Hiroshima Univ. Higashihiroshima‐shi Jpn

• Mattausch Hans

  Hiroshima University

• Mattausch Hans

  Research Institute For Nanodevice And Bio Systems Hiroshima University

• Koide Tetsushi

  Research Institute For Nanodevice And Bio Systems Hiroshima University

• Koide Tetsushi

  Hiroshima Univ. Higashihiroshima‐shi Jpn

• Noda H

  Hitachi Ltd. Kokubunji‐shi Jpn

• Dosaka Katsumi

  Renesas Electronics Corp. Itami‐shi Jpn

• Arimoto Kazutami

  System Core Technology Div. Renesas Technology Corp.

• Morishita Fukashi

  System Core Technology Div. Renesas Technology Corp.

• Morishita Fukashi

  Renesas Technology Corporation

• Arimoto Kazutami

  Renesas Electronics Corp.

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