Regular Fabric of Via Programmable Logic Device Using EXclusive-or Array (VPEX) for EB Direct Writing

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概要

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• The photo-mask cost of standard-cell-based ASICs has been increased so prohibitively that low-volume production LSIs are difficult to fabricate due to high non-recurring engineering (NRE) cost including mask cost. Recently, user-programmable devices, such as FPGAs are started to be used for low-volume consumer products. However, FPGAs cannot be replaced for general purpose because of its lower speed-performance and higher power consumption. In this paper, we propose the user-programmable architecture called VPEX (Via Programmable logic device using EXclusive-or array), in which the hardware logic can be programmed by changing layout patterns on 2 via-layers. The logic element (LE) of VPEX consists of complex-gate-type EXclusive OR (EXOR) and Inverter (NOT) gates. The single LE can output 12 logics which include NOT, Buffer (BUF), all 2-inputs logic functions, 3-inputs AOI21 and inverted-output multiplexer (MUXI) by changing via-1 layout pattern. Furthermore, via-1 layout is optimized for high-throughput EB direct writing, so mask-less programming will be realized in VPEX. We compared the performance of area, speed, and power consumption of VPEX with that of standard-cell-based ASICs and FPGAs. As a result, the speed performance of VPEX was much better than FPGAs and about 1.3-1.6 times worse than standard-cells. We believe that the combination of VPEX architecture and EB direct writing is the best solution for low-volume production LSIs.

• （社）電子情報通信学会の論文
• 2008-04-01

著者

• FUJINO Takeshi

  Department of Electric and Electronic Engineering, Ritsumeikan University

• NAKAMURA Akihiro

  Department of Electrical Engineering, Hiroshima University

• Fujino Takeshi

  Department Of Electric And Electronic Engineering Ritsumeikan University

• Fujino Takeshi

  Department Of Vlsi System Design Ritsumeikan University

• KAWARASAKI Masahide

  Department of VLSI System Design, Ritsumeikan University

• ISHIBASHI Kouta

  Department of VLSI System Design, Ritsumeikan University

• YOSHIKAWA Masaya

  Department of Information Engineering, Meijyou University

• Yoshikawa Masaya

  Department Of Information Engineering Meijyou University

• Ishibashi Kouta

  Department Of Vlsi System Design Ritsumeikan University

• Kawarasaki Masahide

  Department Of Vlsi System Design Ritsumeikan University

• Yoshikawa Masaya

  Department Of Information Engineering Meijo University

• Nakamura Akihiro

  Department Of Vlsi System Design Ritsumeikan University

• Nakamura Akihiro

  Department Of Applied Chemistry And Biotechnology Faculty Of Engineering Yamanashi University

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