A Smart Design Methodology with Distributed Extra Gate-Arrays for Advanced ULSI Memories (Special Issue on LSI Memories)

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概要

• 論文の詳細を見る

• We propose a smart design methodology for advanced ULSI memories to reduce the turn around time(TAT) for circuit revisions with no area penalty. This methodology was executed by distributing extra gate-arrays, which were composed of the n-channel and p-channel transistors, under the power line and the signal line. This method was applied to the development of a 16 Mb DRAM with double metal wiring. The design TAT can be reduced to 1 / 8 using 1500 gates. This design methodology has been confirmed to be very effective.

• 社団法人電子情報通信学会の論文
• 1993-11-25

著者

• ARIMOTO Kazutami

  ULSI Development Center, Mitsubishi Electric Corporation

• HIDAKA Hideto

  ULSI Laboratory, Mitsubishi Electric Corporation

• FUJISHIMA Kazuyasu

  Semiconductor Group, Mitsubishi Electric Corporation

• ASAKURA Mikio

  ULSI Laboratory, Mitsubishi Electric Corporation

• Hidaka H

  Yrp Mobil Telecommunications Key Technol. Res. Lab. Co. Ltd. Yokosuka‐shi Jpn

• Hidaka Hideto

  Ulsi Laboratory Mitsubishi Electric Corporation

• Asakura Mikio

  Ulsi Laboratory Mitsubishi Electric Corporation

• Tsukude Masaki

  Ulsi Laboratory Mitsubishi Electric Corporation

• Fujishima Kazuyasu

  Ulsi Development Center Mitsubishi Electric Corp.

• Fujishima K

  Mitsubishi Electric Co. Itami‐shi Jpn

• Arimoto Kazutami

  Ulsi Development Center Mitsubishi Electric Corporation

関連論文

• Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM (Special Issue on Ultra-High-Speed IC and LSI Technology)
• Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's (Special Issue on ULSI Memory Technology)
• A 0.18 ★m 32 Mb Embedded DRAM Macro for 3-D Graphics Controller
• A Board Level Parallel Test Circuit and a Short Circuit Failure Repair Circuit for High-Density, Low-Power DRAMs (Special Issue on Circuit Technologies for Memory and Analog LSIs)
• A Mixed-Mode Voltage Down Converter with Impedance Adjustment Circuitry for Low-Voltage High-Frequency Memories
• Studies on Phase Change Characteristics of Binary Mixtures of Erythritol and MgCl_2・6H_2O
• New PCMs Prepared from Erythritol-Polyalcohols Mixtures for Latent Heat Storage between 80 and 100℃
• Effect of Ultrasonic Irradiation Parameters on the Supercooling Relaxation Behavior of PCM
• Emerging Memory Solutions for Graphics Applications
• A Line-Mode Test with Data Register for ULSI Memory Architecture (Special Issue on LSI Memories)
• An Automatic Temperature Compensation of Internal Sense Ground for Subquarter Micron DRAM's(Special Issue on the 1994 VLSI Circuits Symposium)
• Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh(Memory, Low-Power LSI and Low-Power IP)
• Dynamic Floating Body Control SOI CMOS for Power Managed Multimedia ULSIs
• A Well-Synchronized Sensing/Equalizing Method for Sub-1.0-V Operating Advanced DRAM's (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
• A Smart Design Methodology with Distributed Extra Gate-Arrays for Advanced ULSI Memories (Special Issue on LSI Memories)
• A Single Chip Multiprocessor Integrated with High Density DRAM
• A Long Data Retention SOI DRAM with the Body Refresh Function (Special Issue on New Concept Device and Novel Architecture LSIs)
• A Blanket Source Line Architecture with Triple Metal for Giga Scale Memory LSIs (Special Issue on ULSI Memory Technology)
• Circuit Technology for Giga-bit/Low Voltage Operating SOI-DRAM (Special Issue on SOI Devices and Their Process Technologies)

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