A Single Chip Multiprocessor Integrated with High Density DRAM
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概要
- 論文の詳細を見る
A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing memory latency and improving memory bandwidth. In this paper we evaluate the performance of a single chip multiprocessor integrated with DRAM when the DRAM is organized as on-chip main memory and as on-chip cache. We compare the performance of this architecture with that of a more conventional chip which only has SRAM-based on-chip cache. The DRAM-based architecture with four processors out-performs the SRAM-based architecture on floating point applications which are effectively parallelized and have large working sets. This performance difference is significantly better than that possible in a uniprocessor DRAM-based architecture, which performs only slightly faster than an SRAM-based architecture on the same applications. In addition, on multiprogrammed workloads, in which independent processes are assigned to every processor in a single chip multiprocessor, the large bandwidth of on-chip DRAM can handle the inter-access contention better. These results demonstrate that a multiprocessor takes better advantage of the large bandwidth provided by the on-chip DRAM than a uniprocessor.
- 社団法人電子情報通信学会の論文
- 1999-08-25
著者
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ARIMOTO Kazutami
ULSI Development Center, Mitsubishi Electric Corporation
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Arimoto Kazutami
Ulsi Development Center Mitsubishi Electric Corporation
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Yamauchi Tadaaki
Ulsi Development Center Mitsubishi Electric Corporation
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HAMMOND Lance
Computer Systems Laboratory, Stanford University
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OLUKOTUN Oyekunle
Computer Systems Laboratory, Stanford University
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Hammond Lance
Computer Systems Laboratory Stanford University
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Olukotun Oyekunle
Computer Systems Laboratory Stanford University
関連論文
- Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM (Special Issue on Ultra-High-Speed IC and LSI Technology)
- Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's (Special Issue on ULSI Memory Technology)
- A 0.18 ★m 32 Mb Embedded DRAM Macro for 3-D Graphics Controller
- Fully Self-Timing Data-Bus Architecture for 64-Mb DRAMs
- A Well-Synchronized Sensing/Equalizing Method for Sub-1.0-V Operating Advanced DRAM's (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
- A Smart Design Methodology with Distributed Extra Gate-Arrays for Advanced ULSI Memories (Special Issue on LSI Memories)
- A Single Chip Multiprocessor Integrated with High Density DRAM
- A Long Data Retention SOI DRAM with the Body Refresh Function (Special Issue on New Concept Device and Novel Architecture LSIs)
- A Blanket Source Line Architecture with Triple Metal for Giga Scale Memory LSIs (Special Issue on ULSI Memory Technology)
- Circuit Technology for Giga-bit/Low Voltage Operating SOI-DRAM (Special Issue on SOI Devices and Their Process Technologies)