An Efficient Self-Timed Queue Architecture for ATM Switch LSIs (Special Issue on Multimedia, Analog and Processing LSIs)
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概要
- 論文の詳細を見る
A new approach to implement queues for controlling ATM switch LSI is presented. In many conventional architecture, external FIFOs are provided for each output link and used to manage the address of the buffer in an ATM switch. We reduce the number of FIFOs by using a self-timed queue with a search circuit that finds the earliest entry for each output link. Using this architecture, number of the FIFOs is reduced to 1/N, where N is the switch size. Delay priority and multicasting can be supported without doubling the number of the queues. This new queue can also be utilized as an ATM switch by itself. Evaluation chip was fabricated using 0.5-μm CMOS process technology. Inter-stage transfer speed over 500 MHz and cycle time over 125 MHz was obtained. This performance is enough for a 622-Mbps 16×16 ATM Switch.
- 社団法人電子情報通信学会の論文
- 1994-12-25
著者
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Matsuda Y
Mitsubishi Electric Corp. Itami‐shi Jpn
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Matsuda Yoshio
System Lsi Laboratory Mitsubishi Electric Corporation
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KONDOH Harufusa
System LSI Laboratory, Mitsubishi Electric Corporation
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Yamanaka Hideaki
Communication Systems Laboratory, Mitsubishi Electric Corporation
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Nakaya M
System Lsi Laboratory Mitsubishi Electric Corporation
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Ishiwaki Masahiko
System LSI Laboratory, Mitsubishi Electric Corporation
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Nakaya Masao
System LSI Laboratory, Mitsubishi Electric Corporation
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Kondoh H
Mitsubishi Electric Corp. Itami‐shi Jpn
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Yamanaka Hideaki
Information Technology R Amp D Center Mitsubishi Electric Corporation
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Ishiwaki Masahiko
System Lsi Laboratory Mitsubishi Electric Corporation
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Matsuda Yoshio
System Lsi Development Center Mitsubishi Electric Corporation
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