Linear Time Calculation of On-Chip Power Distribution Network Capacitance Considering State-Dependence
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概要
- 論文の詳細を見る
A fast calculation tool for state-dependent capacitance of power distribution network is proposed. The proposed method achieves linear time-complexity, which can be more than four orders magnitude faster than a conventional SPICE-based capacitance calculation. Large circuits that have been unanalyzable with the conventional method become analyzable for more comprehensive exploration of capacitance variation. The capacitance obtained with the proposed method agrees SPICE-based method completely (up to 5 digits), and time-linearity is confirmed through numerical experiments on various circuits. The maximum and minimum capacitances are also calculated using average and variance estimation. Calculation times are linear time-complexity, too. The proposed tool facilitates to build an accurate macro model of an LSI.
- 2010-12-01
著者
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Masu K
Research Institute Of Electrical Communication Tohoku University
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Masu Kazuya
Integrated Research Institute
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SATO Takashi
Kyoto University
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Masu Kazuya
東工大
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Yamada Kenta
Nec Electronics Corp. Kawasaki‐shi Jpn
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HAGIWARA Shiho
Integrated Research Institute, Tokyo Institute of Technology
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SATO Takashi
Graduate School of Informatics, Kyoto University
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Yamanaga Koh
Integrated Research Institute Tokyo Institute Of Technology
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Hagiwara Shiho
Integrated Research Institute Tokyo Institute Of Technology
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Sato Takashi
Graduate School Of Informatics Kyoto University
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YAMANAGA Koh
Murata Manufacturing Co., Ltd.
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TAKAHASHI Ryo
The University of Tokyo
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Masu Kazuya
Solutions Research Laboratory Tokyo Institute Of Technology
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