A Three-Stage Inverter-Based Stacked Power Amplifier in 65 nm Complementary Metal Oxide Semiconductor Process
スポンサーリンク
概要
- 論文の詳細を見る
A three-stage inverter-based stacked power amplifier (PA) in complementary metal oxide semiconductor (CMOS) process is proposed to overcome low breakdown voltage problem of scaled CMOS technologies. Unlike previous reported stacked PAs which radio frequency choke (RFC) was inevitable, we proposed stacked nMOS and pMOS transistors which effectively eliminates use of RFC. By properly setting self-biased circuits' and transistors' parameters, output impedance could reach up to 50 \Omega which together with not employing the RFC makes this topology very appealing for the scalable PA realization. As a proof of concept, a three-stage PA using 65 nm CMOS technology is implemented. With a 6 V power supply for the third stage, the fabricated PA shows a small-signal gain of 36 dB, a saturated output power of 16 dBm and a maximum power added efficiency of 10% at 1 GHz. Using a 7.5 V of power supply, saturated output power reaches 18 dBm. To the best of our knowledge, this is the first reported inverter-based stacked PA.
- 2012-02-25
著者
-
Mizuochi Yutaka
Solution Science Research Laboratory (ssrl) Tokyo Institute Of Technology
-
Masu Kazuya
Solutions Research Laboratory Tokyo Institute Of Technology
-
Ishihara Noboru
Solutions Research Laboratory Tokyo Institute Of Technology
-
Ito Hiroyuki
Solutions Research Laboratory, Tokyo Institute of Technology
-
Kiumarsi Hamid
Solutions Research Laboratory, Tokyo Institute of Technology, Yokohama 226-8503, Japan
-
Kiumarsi Hamid
Solutions Research Laboratory, Tokyo Institute of Technology
-
Kiumarsi Hamid
Solutions Research Laboratory Tokyo Institute of Technology
関連論文
- A Universal Equivalent Circuit Model for Ceramic Capacitors
- Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress
- C-12-43 CMOS Power Amplifier in 65nm Technology
- Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits
- 2-Port Modeling Technique for Surface-Mount Passive Components Using Partial Inductance Concept
- A Time-Slicing Ring Oscillator for Capturing Time-Dependent Delay Degradation and Power Supply Voltage Fluctuation
- One-Shot Voltage-Measurement Circuit Utilizing Process Variation
- Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network
- Statistical Modeling of a Via Distribution for Yield Estimation(Interconnect,VLSI Design and CAD Algorithms)
- Wire Length Distribution Model for System LSI(Interconnect, VLSI Design and CAD Algorithms)
- Evaluation of X Architecture Using Interconnect Length Distribution(Interconnect, VLSI Design and CAD Algorithms)
- Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model(Prediction and Analysis, VLSI Design and CAD Algorithms)
- RF Attenuation Characteristics for In Vivo Wireless Healthcare Chip
- Optimization Technique of Number of Interconnect Layers and Circuit Area Based on Wire Length Distribution
- in-vivo Wireless Communication System for Bio MEMS Sensors
- 2.4--10 GHz Low-Noise Injection-Locked Ring Voltage Controlled Oscillator in 90 nm Complementary Metal Oxide Semiconductor
- Linear Time Calculation of On-Chip Power Distribution Network Capacitance Considering State-Dependence
- RF CMOS Integrated Circuit : History, Current Status and Future Prospects
- An Inductorless Phase-Locked Loop with Pulse Injection Locking Technique in 90 nm CMOS (集積回路)
- 0.1V 13GHz Transformer-Based Quadrature Voltage-Controlled Oscillator with a Capacitor Coupling Technique in 90nm Complementary Metal Oxide Semiconductor (Special Issue : Solid State Devices and Materials (2))
- RF signal generator using time domain harmonic suppression technique in 90nm CMOS
- A Three-Stage Inverter-Based Stacked Power Amplifier in 65 nm Complementary Metal Oxide Semiconductor Process
- A Study of Digitally Controllable Radio Frequency Micro Electro Mechanical Systems Inductor
- Planar Solenoidal Inductor in Radio Frequency Micro-Electro-Mechanical Systems Technology for Variable Inductor with Wide Tunable Range and High Quality Factor
- 1.2--17.6 GHz Ring-Oscillator-Based Phase-Locked Loop with Injection Locking in 65 nm Complementary Metal Oxide Semiconductor
- An Inverter-Based Wideband Low-Noise Amplifier in 40 nm Complementary Metal Oxide Semiconductor
- Injection-locked fractional frequency multiplier with automatic reference pulse-selection technique
- A Ring-VCO-Based Injection-Locked Frequency Multiplier with Novel Pulse Generation Technique in 65nm CMOS
- An Inductorless Phase-Locked Loop with Pulse Injection Locking Technique in 90nm CMOS
- Fractionally Injection-Locked Frequency Multiplication Technique with Multi-Phase Ring Voltage-Controlled Oscillator
- C-12-11 Indutors and Transformers on 65 nm CMOS Technology for 60 GHz Applications
- Fractionally Injection-Locked Frequency Multiplication Technique with Multi-Phase Ring Voltage-Controlled Oscillator (Special Issue : Solid State Devices and Materials)
- C-12-23 A1.8 GHz, 2.2 Watt Fully Integrated CMOS Power Amplifier
- A Ring-VCO-Based Injection-Locked Frequency Multiplier with Novel Pulse Generation Technique in 65nm CMOS