Impact of Self-Heating in Wire Interconnection on Timing
スポンサーリンク
概要
- 論文の詳細を見る
This paper evaluates impact of self-heating in wire interconnection on signal propagation delay in an upcoming 32nm process technology, using practical physical parameters. This paper examines a 64-bit data transmission model as one of the most heating cases. Experimental results show that the maximum wire temperature increase due to the self-heating appears in the case where the ratio of interconnect delay becomes largest compared to the driver delay. However, even in the most significant case which induces the maximum temperature rise of 11.0°C, the corresponding increase in the wire resistance is 1.99% and the resulting delay increase is only 1.15%, as for the assumed 32nm process. A part of the impact reduction of wire self-heating on timing comes from the size-effect of nano-scale wires.
- (社)電子情報通信学会の論文
- 2010-03-01
著者
-
KANAMOTO Toshiki
Renesas Technology Corporation
-
HASHIMOTO Masanori
Osaka University
-
SATO Takashi
Kyoto University
-
Sakata Tsuyoshi
Fujitsu Microelectronics Ltd.
-
KUROKAWA Atsushi
Sanyo Semiconductor Co. Ltd.
-
Tanaka Masakazu
Panasonic Corp.
-
Sato T
Photonic Lattice Inc.:niche Tohoku University
-
Masuda Hiroo
Renesas Technol. Corp. Kodaira‐shi Jpn
-
Masuda Hiroo
Renesas Technology Corp.
-
OKUMURA Takaaki
Semiconductor Technology Academic Research Center
-
FURUKAWA Katsuhiro
Jedat Inc.
-
TAKAFUJI Hiroshi
RICOH Company Ltd.
-
HACHIYA Koutaro
Jedat Inc.
-
NAKASHIMA Hidenari
NEC Electronics Corp.
-
Hachiya Kotaro
Jedat Inc.
-
Kurokawa Atsushi
Sanyo Electric Co. Ltd.
-
Hashimoto Masanori
Osaka Univ. Suita‐shi Jpn
-
Kanamoto Toshiki
Mirai‐selete Sagamihara‐shi Jpn
-
Kanamoto Toshiki
Renesas Technology Corp.
-
Kanamoto Toshiki
Renesas Design Corp.
-
Nakashima Hidenari
Integrated Research Institute Tokyo Institute Of Technology
-
Kurokawa Atsushi
Sanyo Electric Co. Ltd
-
Sato Takashi
Institute Of Physics And Tsukuba Research Center For Interdisciplinary Materials Science University
-
Hashimoto Masanori
Osaka Univ.
-
Okumura Takaaki
Semiconductor Technol. Academic Res. Center
-
Masuda Hiroo
Renesas Electronics Corporation, Takasaki, Gunma 370-0021, Japan
関連論文
- Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design(Interconnect,VLSI Design and CAD Algorithms)
- Timing Analysis Considering Spatial Power/Ground Level Variation(Physical Design,VLSI Design and CAD Algorithms)
- A Universal Equivalent Circuit Model for Ceramic Capacitors
- Timing Analysis Considering Temporal Supply Voltage Fluctuation
- Successive Pad Assignment for Minimizing Supply Voltage Drop(Power/Ground Network, VLSI Design and CAD Algorithms)
- A Fast Characterizing Method for Large Embedded Memory Modules on SoC(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures(Interconnect, VLSI Design and CAD Algorithms)
- Inter-Layer Screening Length to Electric Field in Thin Graphite Film
- Coulomb Blockade Oscillations in Narrow Corrugated Graphite Ribbons
- Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model