Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model
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概要
- 論文の詳細を見る
In deep submicron designs, predicting gate delays with interconnect load is a noteworthy work for Static Timing Analysis (STA). The effective capacitance Ceff concept and the Thevenin model that replaces the gate with a linear resistor and a voltage source are usually used to calculate the delay of gate with interconnect load. In conventional methods, it is not considered that the charges transferred into interconnect load and Ceff in the Thevenin model are not equal. The charge difference between interconnect load and Ceff has the large influence to the accuracy of computing Ceff. In this paper, an advanced effective capacitance model is proposed to consider the above problem in the Thevenin model, where the influence of the charge difference is modeled as one part of the effective capacitance to compute the gate delay. Experimental results show a significant improvement in accuracy when the charge difference between interconnect load and Ceff is considered.
- （社）電子情報通信学会の論文
- 2009-10-01
著者
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INOUE Yasuaki
Graduate School of Information, Production and Systems, Waseda University
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Huang Zhangcai
Research Center Of Information Production And Systems Waseda University
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JIANG Minglu
Graduate School of Production, Information and Systems, Waseda University
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HUANG Zhangcai
Fukuoka Industry, Science and Technology Foundation
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KUROKAWA Atsushi
Sanyo Semiconductor Co. Ltd.
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FANG Shuai
Hitachi-LG Storage, Inc.
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Fang Shuai
Hitachi-lg Storage Inc.
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Jiang Minglu
Graduate School Of Information Production And Systems Waseda University
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Inoue Yasuaki
Graduate School Of Information Production And Systems Waseda University
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Inoue Yasuaki
Graduate School Of Ips Waseda University
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Kurokawa Atsushi
Sanyo Electric Co. Ltd.
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Huang Zhangcai
Fukuoka Industry Science And Technology Foundation
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Kurokawa Atsushi
Sanyo Electric Co. Ltd
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