Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew
スポンサーリンク
概要
- 論文の詳細を見る
In deep submicron designs, predicting gate slews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance Ceff concept is usually used to calculate the gate delay of the interconnect loads. Many Ceff algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a Ceff algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating Ceff of interconnect load for gate slew. The simulation results demonstrate a significant improvement in accuracy.
- 社団法人電子情報通信学会の論文
- 2005-09-08
著者
-
Huang Zhangcai
Research Center Of Information Production And Systems Waseda University
-
HUANG Zhangcai
The Graduate School of Information, Production and Systems, Waseda University
-
KUROKAWA Atsushi
The Semiconductor Technology Academic Research Center (STAC)
-
INOUE Yasuaki
The Graduate School of Information, Production and Systems, Waseda University
関連論文
- A Low-Power Sub-1-V Low-Voltage Reference Using Body Effect(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model
- A Highly Linear and Wide Input Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback
- An advanced effective capacitance model considering input waveform effect (第21回 回路とシステム軽井沢ワークショップ論文集) -- (ばらつき関連技術)
- An Effective SPICE3 Implementation of the Compound Element Pseudo-Transient Algorithm(Nonlinear Circuits,Nonlinear Theory and its Applications)
- Behavioral Circuit Macromodeling and Analog LSI Implementation for Automobile Engine Intake System(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- An Effective Pseudo-Transient Algorithm for Finding DC Solutions of Nonlinear Circuits(Modelling, Systems and Simulation,Nonlinear Theory and its Applications)
- Determination of Interconnect Structural Parameters for Best-and Worst-Case Delays(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- A highly linear and wide dynamic range four-quadrant CMOS analog multiplier using active feedback (アナログ要素回路)
- Behavior macromodeling of analog LSI implementation for automobile intake system (回路とシステムの理論)
- Calculating the effective capacitance for interconnect loads based on thevenin model (VLSIのノイズ・タイミング解析)
- Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance(Interconnect, VLSI Design and CAD Algorithms)
- Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew(Prediction and Analysis, VLSI Design and CAD Algorithms)
- A Self-Biased Low-Voltage Low-Power Current/Voltage Reference Circuit With Very Low Temperature Dependence by Using Back-Gate Connection MOSFET
- A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads(Nonlinear Theory and its Applications)
- Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew
- Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew
- Finding All Solutions of Nonlinear Equations Using Inverses of Approximate Jacobian Matrices
- A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect