Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay(<Special Section>Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
スポンサーリンク
概要
- 論文の詳細を見る
The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of the input-to-output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.
- 社団法人電子情報通信学会の論文
- 2006-04-01
著者
-
Yang Yun
Graduate School Of Information Production And Systems Waseda University
-
INOUE Yasuaki
Graduate School of Information, Production and Systems, Waseda University
-
HUANG Zhangcai
Graduate School of Information, Production and Systems, Waseda University
-
Yang Yun
Waseda Univ. Kitakyushu‐shi Jpn
-
Huang Zhangcai
Research Center Of Information Production And Systems Waseda University
-
YU Hong
Graduate School of Information, Production and Systems, Waseda University
-
KUROKAWA Atsushi
Semiconductor Technology Academic Research Center (STARC)
-
Yu Hong
Graduate School Of Information Production And Systems Waseda University
-
Inoue Yasuaki
Graduate School Of Information Production And Systems Waseda University
-
Huang Zhangcai
Graduate School Of Information Production And Systems Waseda University
-
Inoue Yasuaki
Graduate School Of Ips Waseda University
-
Kurokawa Atsushi
Sanyo Electric Co. Ltd.
-
Yu Hong
Graduate School Of Information Production And System Waseda University
-
Kurokawa Atsushi
Sanyo Electric Co. Ltd
関連論文
- A Low-Power Sub-1-V Low-Voltage Reference Using Body Effect(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- A Low-Power High-Speed Rail-to-Rail Class-B Buffer Amplifier for LCD Column Driver
- A Low-Power High-Speed Rail-to-Rail Class-B Output Buffer for TFT-LCD Source Driver
- A Low-Power High-Speed Rail-to-Rail Class-B Buffer Amplifier for LCD Column Driver
- A Low-Power High-Speed Rail-to-Rail Class-B Output Buffer for TFT-LCD Source Driver
- A Low-Power High-Speed Rail-to-Rail Class-B Output Buffer for TFT-LCD Source Driver
- The Optimal Architecture Design of Two-Dimension Matrix Multiplication Jumping Systolic Array
- Memristor Model for SPICE
- Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model
- A Highly Linear and Wide Input Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback
- An advanced effective capacitance model considering input waveform effect (第21回 回路とシステム軽井沢ワークショップ論文集) -- (ばらつき関連技術)
- An Effective SPICE3 Implementation of the Compound Element Pseudo-Transient Algorithm(Nonlinear Circuits,Nonlinear Theory and its Applications)
- Behavioral Circuit Macromodeling and Analog LSI Implementation for Automobile Engine Intake System(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- An Effective Pseudo-Transient Algorithm for Finding DC Solutions of Nonlinear Circuits(Modelling, Systems and Simulation,Nonlinear Theory and its Applications)
- Determination of Interconnect Structural Parameters for Best-and Worst-Case Delays(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- A highly linear and wide dynamic range four-quadrant CMOS analog multiplier using active feedback (アナログ要素回路)
- Behavior macromodeling of analog LSI implementation for automobile intake system (回路とシステムの理論)
- Calculating the effective capacitance for interconnect loads based on thevenin model (VLSIのノイズ・タイミング解析)
- Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance(Interconnect, VLSI Design and CAD Algorithms)
- Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew(Prediction and Analysis, VLSI Design and CAD Algorithms)
- A Self-Biased Low-Voltage Low-Power Current/Voltage Reference Circuit With Very Low Temperature Dependence by Using Back-Gate Connection MOSFET
- A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads(Nonlinear Theory and its Applications)
- Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew
- Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew
- A Pseudo-Transient Method Using Compound Elements for Finding DC Operating Points
- A pseudo-transient method using compound elements for finding DC operating points (回路とシステムの理論)
- An Effective Pseudo-transient Algorithm for Finding DC Operating Points of Nonlinear Circuits
- An Energy Management Circuit for Self-Powered Ubiquitous Sensor Modules Using Vibration-Based Energy(Nonlinear Circuits,Nonlinear Theory and its Applications)
- Impact of Self-Heating in Wire Interconnection on Timing
- An Approach for Reducing Leakage Current Variation due to Manufacturing Variability
- Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations
- Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances(Parasitics and Noise)(VLSI Design and CAD Algorithms)
- Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances
- Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects
- Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation(Interconnect,VLSI Design and CAD Algorithms)
- Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills(Interconnect, VLSI Design and CAD Algorithms)
- A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills(VLSI Design Technology and CAD)
- A Novel Expression of Spatial Correlation by a Random Curved Surface Model and Its Application to LSI Design
- Efficient Large Scale Integration Power/Ground Network Optimization Based on Grid Genetic Algorithm(Power/Ground Network, VLSI Design and CAD Algorithms)
- Practical Redundant-Via Insertion Method Considering Manufacturing Variability and Reliability
- An Initial Solution Algorithm for Globally Convergent Homotopy Methods(Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
- A Bulk-Current Model for Advanced MOSFET Technologies Without Binning : Substrate Current and Fowler-Nordheim Current
- A Gate-Current Model for Advanced MOSFET Technologies Implemented into HiSIM2
- A PN Junction-Current Model for Advanced MOSFET Technologies
- A 12-bit 3.7-Msample/s Pipelined A/D Converter Based on the Novel Capacitor Mismatch Calibration Technique
- AS-2-2 An Algorithmic Stage Based on the Novel Capacitor Mismatch Calibration Technique
- An algorithmic stage based on the novel capacitor mismatch calibration technique (第21回 回路とシステム軽井沢ワークショップ論文集) -- (ADC(2))
- A 15-bit 10-Msample/s Pipelined A/D Converter Based on Incomplete Settling Principle(Modelling, Systems and Simulation,Nonlinear Theory and its Applications)
- A Globally Convergent Method for Finding DC Solutions of MOS Transistor Circuits
- An Effective Implementation of the Compound Element Pseudo-transient Algorithm on SPICE3
- A Globally Convergent Method for Finding DC Solutions of MOS Transistor Circuits
- An Effective Implementation of the Compound Element Pseudo-transient Algorithm on SPICE3
- Simple Analytical Formulas for Estimating IR-Drops in an Early Design Stage
- Prevention in a Chip of EMI Noise Caused by X'tal Oscillator
- An Efficient Homotopy Method for Finding DC Operating Points of Nonlinear Circuits(Nonlinear Theory and its Applications)
- A Homotopy Method Using a Nonlinear Auxiliary Function for Solving Transistor Circuits(General and Nonlinear Circuits and Systems, Recent Advances in Circuits and Systems-Part 1)
- Path Following Circuits : SPICE-Oriented Numerical Methods Where Formulas are Described by Circuits(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
- Theorems on the Unique Initial Solution for Globally Convergent Homotopy Methods(Numerical Caluculation)(Nonlinear Theory and its Applications)
- Efficient Hybrid Grid Synthesis Method Based on Genetic Algorithm for Power/Ground Network Optimization with Dynamic Signal Consideration
- A 15-bit 10-Msample/s pipelined A/D converter based on incomplete settling principle (変換回路)
- A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect
- A sub-0.3V highly efficient CMOS rectifier for energy harvesting applications
- A Globally Convergent Nonlinear Homotopy Method for MOS Transistor Circuits
- An Effective and Globally Convergent Newton Fixed-Point Homotopy Method for MOS Transistor Circuits
- A low voltage CMOS rectifier for low power battery-less devices
- Effective Implementation and Embedding Algorithms of CEPTA Method for Finding DC Operating Points