Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew(Prediction and Analysis, <Special Section>VLSI Design and CAD Algorithms)

概要

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In deep submicron designs, predicting gate slews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance C_<eff> concept is usually used to calculate the gate delay of interconnect loads. Many C_<eff> algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a C_<eff> algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating the C_<eff> of interconnect load for gate slew. We firstly establish a new expression for C_<eff> in 0.8Vdd point. Then the Integration Approximation method is used to calculate the value of C_<eff> in 0.8Vdd point. In this method, the integration of a complicated nonlinear gate output is approximated with that of a piecewise linear waveform. Based on the value of C_<eff> in 0.8Vdd point, C_<eff> of interconnect load for gate slew is obtained. The simulation results demonstrate a significant improvement in accuracy.
社団法人電子情報通信学会の論文
2005-12-01