Inoue Yasuaki | Graduate School Of Ips Waseda University

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概要

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著作論文

A Low-Power Sub-1-V Low-Voltage Reference Using Body Effect(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
A Low-Power High-Speed Rail-to-Rail Class-B Buffer Amplifier for LCD Column Driver
A Low-Power High-Speed Rail-to-Rail Class-B Output Buffer for TFT-LCD Source Driver
A Low-Power High-Speed Rail-to-Rail Class-B Buffer Amplifier for LCD Column Driver
A Low-Power High-Speed Rail-to-Rail Class-B Output Buffer for TFT-LCD Source Driver
A Low-Power High-Speed Rail-to-Rail Class-B Output Buffer for TFT-LCD Source Driver
Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model
A Highly Linear and Wide Input Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback
An Effective SPICE3 Implementation of the Compound Element Pseudo-Transient Algorithm(Nonlinear Circuits,Nonlinear Theory and its Applications)
Behavioral Circuit Macromodeling and Analog LSI Implementation for Automobile Engine Intake System(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
An Effective Pseudo-Transient Algorithm for Finding DC Solutions of Nonlinear Circuits(Modelling, Systems and Simulation,Nonlinear Theory and its Applications)
Determination of Interconnect Structural Parameters for Best-and Worst-Case Delays(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
A highly linear and wide dynamic range four-quadrant CMOS analog multiplier using active feedback (アナログ要素回路)
Behavior macromodeling of analog LSI implementation for automobile intake system (回路とシステムの理論)
Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance(Interconnect, VLSI Design and CAD Algorithms)
Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew(Prediction and Analysis, VLSI Design and CAD Algorithms)
A Self-Biased Low-Voltage Low-Power Current/Voltage Reference Circuit With Very Low Temperature Dependence by Using Back-Gate Connection MOSFET
A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads(Nonlinear Theory and its Applications)
A Pseudo-Transient Method Using Compound Elements for Finding DC Operating Points
A pseudo-transient method using compound elements for finding DC operating points (回路とシステムの理論)
An Effective Pseudo-transient Algorithm for Finding DC Operating Points of Nonlinear Circuits
An Energy Management Circuit for Self-Powered Ubiquitous Sensor Modules Using Vibration-Based Energy(Nonlinear Circuits,Nonlinear Theory and its Applications)
Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills(Interconnect, VLSI Design and CAD Algorithms)
A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills(VLSI Design Technology and CAD)
Efficient Large Scale Integration Power/Ground Network Optimization Based on Grid Genetic Algorithm(Power/Ground Network, VLSI Design and CAD Algorithms)
A Bulk-Current Model for Advanced MOSFET Technologies Without Binning : Substrate Current and Fowler-Nordheim Current
A Gate-Current Model for Advanced MOSFET Technologies Implemented into HiSIM2
A PN Junction-Current Model for Advanced MOSFET Technologies
A 12-bit 3.7-Msample/s Pipelined A/D Converter Based on the Novel Capacitor Mismatch Calibration Technique
AS-2-2 An Algorithmic Stage Based on the Novel Capacitor Mismatch Calibration Technique
An algorithmic stage based on the novel capacitor mismatch calibration technique (第21回回路とシステム軽井沢ワークショップ論文集) -- (ADC(2))
A 15-bit 10-Msample/s Pipelined A/D Converter Based on Incomplete Settling Principle(Modelling, Systems and Simulation,Nonlinear Theory and its Applications)
A Globally Convergent Method for Finding DC Solutions of MOS Transistor Circuits
An Effective Implementation of the Compound Element Pseudo-transient Algorithm on SPICE3
A Globally Convergent Method for Finding DC Solutions of MOS Transistor Circuits
An Effective Implementation of the Compound Element Pseudo-transient Algorithm on SPICE3
A 15-bit 10-Msample/s pipelined A/D converter based on incomplete settling principle (変換回路)
A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect

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