Kanamoto Toshiki | Renesas Technology Corp.

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概要

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著作論文

A Fast Characterizing Method for Large Embedded Memory Modules on SoC(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures(Interconnect, VLSI Design and CAD Algorithms)
Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Impact of Self-Heating in Wire Interconnection on Timing
An Approach for Reducing Leakage Current Variation due to Manufacturing Variability
Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations
Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation(Interconnect,VLSI Design and CAD Algorithms)
Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills(Interconnect, VLSI Design and CAD Algorithms)
A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills(VLSI Design Technology and CAD)
Impact of Well Edge Proximity Effect on Timing

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