Masuda Hiroo | Semiconductor Technology Academic Research Center (starc)

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著作論文

100 nm-MOSFET Model for Circuit Simulation : Challenges and Solutions(Devices and Circuits for Next Generation Multi-Media Communication Systems)
Design Guidelines and Process Quality Improvement for Treatment of Device Variations in an LSI Chip(Microelectronic Test Structures)
Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances(Parasitics and Noise)(VLSI Design and CAD Algorithms)
Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances
Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects
A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills(VLSI Design Technology and CAD)
Measurement of Inner-chip Variation and Signal Integrity By a 90-nm Large-scale TEG
Measurement of Inner-chip Variation and Signal Integrity By a 90-nm Large-scale TEG
100 nm-MOSFET Model for Circuit Simulation : Challenges and Solutions

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