A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills(VLSI Design Technology and CAD)

スポンサーリンク

概要

• 論文の詳細を見る

• We present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances for system-on-chip (SoC) designs. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy metal fills on the parasitic capacitance, signal delay, and crosstalk noise. Moreover, we address that interlayer dummy metal fills have more significant influences than intralayer ones in terms of the impact on coupling capacitances. When dummy metal fills are ignored, the error of capacitance extraction can be more than 30%, whereas the error of the proposed method is less than about 10% for many practical geometries. We also demonstrate, by comparison with capacitance results measured for a 90-nm test chip, that the error of the proposed method is less than 8%.

• 社団法人電子情報通信学会の論文
• 2005-11-01

著者

• KANAMOTO Toshiki

  Renesas Technology Corporation

• KASEBE Akira

  Meitec Corp.

• INOUE Yasuaki

  Waseda University

• KUROKAWA Atsushi

  Semiconductor Technology Academic Research Center (STARC)

• Masuda Hiroo

  Semiconductor Technology Academic Research Center (starc)

• Masuda Hiroo

  Renesas Technology Corp.

• Masuda Hiroo

  Semiconductor Technology Academic Research Center

• Inoue Yasuaki

  Graduate School Of Ips Waseda University

• Kurokawa Atsushi

  Sanyo Electric Co. Ltd.

• Kanamoto Toshiki

  Mirai‐selete Sagamihara‐shi Jpn

• Kanamoto Toshiki

  Renesas Technology Corp.

• Kanamoto Toshiki

  Renesas Design Corp.

• Kurokawa Atsushi

  Sanyo Electric Co. Ltd

関連論文

• Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design(Interconnect,VLSI Design and CAD Algorithms)
• A Low-Power Sub-1-V Low-Voltage Reference Using Body Effect(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
• A Low-Power High-Speed Rail-to-Rail Class-B Buffer Amplifier for LCD Column Driver
• A Low-Power High-Speed Rail-to-Rail Class-B Output Buffer for TFT-LCD Source Driver
• A Low-Power High-Speed Rail-to-Rail Class-B Buffer Amplifier for LCD Column Driver
• A Low-Power High-Speed Rail-to-Rail Class-B Output Buffer for TFT-LCD Source Driver
• A Low-Power High-Speed Rail-to-Rail Class-B Output Buffer for TFT-LCD Source Driver
• A Fast Characterizing Method for Large Embedded Memory Modules on SoC(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
• A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures(Interconnect, VLSI Design and CAD Algorithms)
• Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model
• A Highly Linear and Wide Input Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback
• An advanced effective capacitance model considering input waveform effect (第21回 回路とシステム軽井沢ワークショップ論文集) -- (ばらつき関連技術)
• An Effective SPICE3 Implementation of the Compound Element Pseudo-Transient Algorithm(Nonlinear Circuits,Nonlinear Theory and its Applications)
• Behavioral Circuit Macromodeling and Analog LSI Implementation for Automobile Engine Intake System(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
• An Effective Pseudo-Transient Algorithm for Finding DC Solutions of Nonlinear Circuits(Modelling, Systems and Simulation,Nonlinear Theory and its Applications)
• Determination of Interconnect Structural Parameters for Best-and Worst-Case Delays(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
• Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
• Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
• A highly linear and wide dynamic range four-quadrant CMOS analog multiplier using active feedback (アナログ要素回路)
• Behavior macromodeling of analog LSI implementation for automobile intake system (回路とシステムの理論)
• Calculating the effective capacitance for interconnect loads based on thevenin model (VLSIのノイズ・タイミング解析)
• Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance(Interconnect, VLSI Design and CAD Algorithms)
• Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew(Prediction and Analysis, VLSI Design and CAD Algorithms)
• A Self-Biased Low-Voltage Low-Power Current/Voltage Reference Circuit With Very Low Temperature Dependence by Using Back-Gate Connection MOSFET
• A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads(Nonlinear Theory and its Applications)
• Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew
• A Pseudo-Transient Method Using Compound Elements for Finding DC Operating Points
• A pseudo-transient method using compound elements for finding DC operating points (回路とシステムの理論)
• An Effective Pseudo-transient Algorithm for Finding DC Operating Points of Nonlinear Circuits
• Delay Library Generation with High Efficiency and Accuracy on the Basis of RSM (Special lssue on SISPAD'99)
• A New High-Speed Low-Voltage Charge Pump for PLL Applications
• A New Hierarchical RSM for TCAD-Based Device Design in 0.4μm CMOS Development (Special Issue on Microelectronic Test Structure)
• An Energy Management Circuit for Self-Powered Ubiquitous Sensor Modules Using Vibration-Based Energy(Nonlinear Circuits,Nonlinear Theory and its Applications)
• 100 nm-MOSFET Model for Circuit Simulation : Challenges and Solutions(Devices and Circuits for Next Generation Multi-Media Communication Systems)
• Design Guidelines and Process Quality Improvement for Treatment of Device Variations in an LSI Chip(Microelectronic Test Structures)
• A Parallel Method to Extract Critical Areas of Net Pairs for Diagnosing Bridge Faults
• Impact of Self-Heating in Wire Interconnection on Timing
• An Approach for Reducing Leakage Current Variation due to Manufacturing Variability
• Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations
• Proposal of Metrics for SSTA Accuracy Evaluation(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
• On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature(Simulation and Verification,VLSI Design and CAD Algorithms)
• On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design(Prediction and Analysis, VLSI Design and CAD Algorithms)
• Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances(Parasitics and Noise)(VLSI Design and CAD Algorithms)
• Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances
• Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects
• Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation(Interconnect,VLSI Design and CAD Algorithms)
• Modeling of Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor for Accurate Prediction of Junction Condition on Device Characteristics
• Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills(Interconnect, VLSI Design and CAD Algorithms)
• A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills(VLSI Design Technology and CAD)
• Modeling and Simulation on Degradation of Submicron NMOSFET Current Drive due to Velocity-Saturation Effects (Special Issue on 1993 VLSI Process and Device Modeling Workshop (VPAD93))
• Evaluation of Two-Dimensional Transient Enhanced Diffusion of Phosphorus during Shallow Junction Formation (Special Issue on 1993 VLSI Process and Device Modeling Workshop (VPAD93))
• Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis
• Measurement of Inner-chip Variation and Signal Integrity By a 90-nm Large-scale TEG
• Measurement of Inner-chip Variation and Signal Integrity By a 90-nm Large-scale TEG
• Efficient Large Scale Integration Power/Ground Network Optimization Based on Grid Genetic Algorithm(Power/Ground Network, VLSI Design and CAD Algorithms)
• 100 nm-MOSFET Model for Circuit Simulation : Challenges and Solutions
• Practical Redundant-Via Insertion Method Considering Manufacturing Variability and Reliability
• A Bulk-Current Model for Advanced MOSFET Technologies Without Binning : Substrate Current and Fowler-Nordheim Current
• A Gate-Current Model for Advanced MOSFET Technologies Implemented into HiSIM2
• A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance
• A PN Junction-Current Model for Advanced MOSFET Technologies
• A 12-bit 3.7-Msample/s Pipelined A/D Converter Based on the Novel Capacitor Mismatch Calibration Technique
• AS-2-2 An Algorithmic Stage Based on the Novel Capacitor Mismatch Calibration Technique
• An algorithmic stage based on the novel capacitor mismatch calibration technique (第21回 回路とシステム軽井沢ワークショップ論文集) -- (ADC(2))
• A 15-bit 10-Msample/s Pipelined A/D Converter Based on Incomplete Settling Principle(Modelling, Systems and Simulation,Nonlinear Theory and its Applications)
• A Globally Convergent Method for Finding DC Solutions of MOS Transistor Circuits
• An Effective Implementation of the Compound Element Pseudo-transient Algorithm on SPICE3
• A Globally Convergent Method for Finding DC Solutions of MOS Transistor Circuits
• An Effective Implementation of the Compound Element Pseudo-transient Algorithm on SPICE3
• Simple Analytical Formulas for Estimating IR-Drops in an Early Design Stage
• AS-2-1 A 45nm Stable Dynamic Standby Mode SRAM for Leakage Power Suppression
• Prevention in a Chip of EMI Noise Caused by X'tal Oscillator
• An Efficient Homotopy Method for Solving Nonlinear Circiuts
• Impact of Well Edge Proximity Effect on Timing
• A 15-bit 10-Msample/s pipelined A/D converter based on incomplete settling principle (変換回路)
• A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect
• A GIDL-Current Model for Advanced MOSFET Technologies without Binning

もっと見る 閉じる

スポンサーリンク