A Fast Characterizing Method for Large Embedded Memory Modules on SoC(<Special Section>Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
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概要
- 論文の詳細を見る
This paper proposes a new efficient method of characterizing a memory compiler in order to reduce the computation time and remove human error. The new features that make our method greatly efficient are the following three points: (1) high-speed circuit simulation of the whole memory module using a hierarchical LPE (Layout Parasitic Extractor) and a hierarchical circuit simulator, (2) automatic generation of circuit simulation input data from corresponding parameterized description termed the template file, and (3) carefully selected environmental conditions of circuit level simulator and minimizing the number of runs of it. We demonstrate the effectiveness of the proposed method by application to the single-port SRAM generators using 90nm CMOS technology.
- 社団法人電子情報通信学会の論文
- 2007-04-01
著者
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Terai Masayuki
Faculty Of Informatics Osaka Gakuin University
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KANAMOTO Toshiki
Renesas Technology Corporation
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OMURA Masahiko
Renesas Technology Corp.
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TSUKAMOTO Michiko
Renesas Technology Corp.
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SHIROTA Mitsutoshi
Renesas Technology Corp.
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NAKAJIMA Takashi
Renesas Technology Corp.
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Kanamoto Toshiki
Mirai‐selete Sagamihara‐shi Jpn
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Kanamoto Toshiki
Renesas Technology Corp.
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Kanamoto Toshiki
Renesas Design Corp.
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