Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation(Interconnect,<Special Section>VLSI Design and CAD Algorithms)

スポンサーリンク

概要

• 論文の詳細を見る

• In this letter, we discuss the impact of intrinsic error in parasitic capacitance extraction programs which are commonly used in today's SoC design flows. Most of the extraction programs use pattern-matching methods which introduces an improvable error factor due to the pattern interpolation, and an intrinsically inescapable error factor from the difference of boundary conditions in the electro-magnetic field solver. Here, we study impact of the intrinsic error on timing and crosstalk noise estimation. We experimentally show that the resulting delay and noise estimation errors show a scatter which is normally distributed. Values of the standard deviations will help designers consider the intrinsic error compared with other variation factors.

• 2006-12-01

著者

• KANAMOTO Toshiki

  Renesas Technology Corporation

• HASHIMOTO Masanori

  Osaka University

• KUROKAWA Atsushi

  STARC

• Masuda Hiroo

  Renesas Technology Corp.

• KOBAYASHI Hiroyuki

  Nihon Synopsys Co., Ltd.

• HACHIYA Koutaro

  NEC Electronics Corp.

• Hachiya Kotaro

  Jedat Inc.

• AKUTSU Shigekiyo

  Oki Electric Industry Co., Ltd.

• NAKABAYASHI Tamiyo

  SHARP Corporation

• ICHINOMIYA Takahiro

  Matsushita Electric Industrial Co., Ltd.

• ISHIKAWA Hiroshi

  Sequence Design, Inc.

• MUROMOTO Sakae

  Cadence Design Systems

• Kurokawa Atsushi

  Sanyo Electric Co. Ltd.

• Hashimoto Masanori

  Osaka Univ. Suita‐shi Jpn

• Akutsu Shigekiyo

  Oki Electric Industry Co. Ltd.

• Kanamoto Toshiki

  Mirai‐selete Sagamihara‐shi Jpn

• Kanamoto Toshiki

  Renesas Technology Corp.

• Kanamoto Toshiki

  Renesas Design Corp.

• Ichinomiya Takahiro

  Matsushita Electric Industrial Co. Ltd.

• Kobayashi Hiroyuki

  Nihon Synopsys Co. Ltd.

• Kurokawa Atsushi

  Sanyo Electric Co. Ltd

• Ishikawa Hiroshi

  Sequence Design Inc.

• Hashimoto Masanori

  Osaka Univ.

関連論文

• Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design(Interconnect,VLSI Design and CAD Algorithms)
• Timing Analysis Considering Spatial Power/Ground Level Variation(Physical Design,VLSI Design and CAD Algorithms)
• Timing Analysis Considering Temporal Supply Voltage Fluctuation
• Successive Pad Assignment for Minimizing Supply Voltage Drop(Power/Ground Network, VLSI Design and CAD Algorithms)
• A Fast Characterizing Method for Large Embedded Memory Modules on SoC(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
• A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures(Interconnect, VLSI Design and CAD Algorithms)
• Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model
• An advanced effective capacitance model considering input waveform effect (第21回 回路とシステム軽井沢ワークショップ論文集) -- (ばらつき関連技術)
• Determination of Interconnect Structural Parameters for Best-and Worst-Case Delays(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
• Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
• Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
• Calculating the effective capacitance for interconnect loads based on thevenin model (VLSIのノイズ・タイミング解析)
• Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance(Interconnect, VLSI Design and CAD Algorithms)
• Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew(Prediction and Analysis, VLSI Design and CAD Algorithms)
• A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads(Nonlinear Theory and its Applications)
• Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew
• Transistor Sizing of LCD Driver Circuit for Technology Migration(Circuit Synthesis,VLSI Design and CAD Algorithms)
• A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays(Circuit Synthesis,VLSI Design and CAD Algorithms)
• Statistical Analysis of Clock Skew Variation in H-Tree Structure(Prediction and Analysis, VLSI Design and CAD Algorithms)
• Delay Library Generation with High Efficiency and Accuracy on the Basis of RSM (Special lssue on SISPAD'99)
• A New Hierarchical RSM for TCAD-Based Device Design in 0.4μm CMOS Development (Special Issue on Microelectronic Test Structure)
• A Parallel Method to Extract Critical Areas of Net Pairs for Diagnosing Bridge Faults
• Impact of Self-Heating in Wire Interconnection on Timing
• An Approach for Reducing Leakage Current Variation due to Manufacturing Variability
• Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations
• Proposal of Metrics for SSTA Accuracy Evaluation(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
• On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature(Simulation and Verification,VLSI Design and CAD Algorithms)
• A Method to Derive SSO Design Rule Considering Jitter Constraint(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
• On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design(Prediction and Analysis, VLSI Design and CAD Algorithms)
• Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances(Parasitics and Noise)(VLSI Design and CAD Algorithms)
• Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances
• Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects
• Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation(Interconnect,VLSI Design and CAD Algorithms)
• Modeling of Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor for Accurate Prediction of Junction Condition on Device Characteristics
• Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills(Interconnect, VLSI Design and CAD Algorithms)
• A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills(VLSI Design Technology and CAD)
• Modeling and Simulation on Degradation of Submicron NMOSFET Current Drive due to Velocity-Saturation Effects (Special Issue on 1993 VLSI Process and Device Modeling Workshop (VPAD93))
• Evaluation of Two-Dimensional Transient Enhanced Diffusion of Phosphorus during Shallow Junction Formation (Special Issue on 1993 VLSI Process and Device Modeling Workshop (VPAD93))
• Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis
• Efficient Large Scale Integration Power/Ground Network Optimization Based on Grid Genetic Algorithm(Power/Ground Network, VLSI Design and CAD Algorithms)
• Practical Redundant-Via Insertion Method Considering Manufacturing Variability and Reliability
• A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance
• Gate Delay Estimation in STA under Dynamic Power Supply Noise
• Simple Analytical Formulas for Estimating IR-Drops in an Early Design Stage
• Prevention in a Chip of EMI Noise Caused by X'tal Oscillator
• Fast Methods to Estimate Clock Jitter due to Power Supply Noise(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
• Impact of Well Edge Proximity Effect on Timing
• A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect
• Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise

もっと見る 閉じる

スポンサーリンク