Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew

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概要

• 論文の詳細を見る

• In deep submicron designs, predicting gate slews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance Ceff concept is usually used to calculate the gate delay of the interconnect loads. Many Ceff algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a Ceff algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating Ceff of interconnect load for gate slew. The simulation results demonstrate a significant improvement in accuracy.

• 社団法人電子情報通信学会の論文
• 2005-09-08

著者

• Huang Zhangcai

  Research Center Of Information Production And Systems Waseda University

• HUANG Zhangcai

  The Graduate School of Information, Production and Systems, Waseda University

• KUROKAWA Atsushi

  The Semiconductor Technology Academic Research Center (STAC)

• INOUE Yasuaki

  The Graduate School of Information, Production and Systems, Waseda University

• Kurokawa Atsushi

  Sanyo Electric Co. Ltd.

• Kurokawa Atsushi

  Sanyo Electric Co. Ltd

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