Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance(Interconnect, <Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• Simple closed-form expressions for efficiently calculating on-chip interconnect capacitances are presented. The formulas are expressed with second-order polynomial functions which do not include exponential functions. The runtime of the proposed formulas is about 2-10 times faster than those of existing formulas. The root mean square (RMS) errors of the proposed formulas are within 1.5%, 1.3%, 3.1%, and 4.6% of the results obtained by a field solver for structures with one line above a ground plane, one line between ground planes, three lines above a ground plane, and three lines between ground planes, respectively. The proposed formulas are also superior in accuracy to existing formulas.

• 社団法人電子情報通信学会の論文
• 2005-12-01

著者

• HASHIMOTO Masanori

  Osaka University

• Yang Yun

  Waseda Univ. Kitakyushu‐shi Jpn

• Huang Zhangcai

  Research Center Of Information Production And Systems Waseda University

• KUROKAWA Atsushi

  STARC

• MASUDA Hiroo

  STARC

• KASEBE Akira

  Meitec Corp.

• HUANG Zhangcai

  Waseda University

• INOUE Yasuaki

  Waseda University

• INAGAKI Ryosuke

  STARC

• Huang Zhangcai

  Waseda Univ. Kitakyushu‐shi Jpn

• Masuda Hiroo

  Renesas Technology Corp.

• Inagaki Ryosuke

  Graduate School Of Ips Waseda University

• Inagaki Ryosuke

  Starc:waseda University

• Inoue Yasuaki

  Graduate School Of Ips Waseda University

• Kurokawa Atsushi

  Sanyo Electric Co. Ltd.

• Hashimoto Masanori

  Osaka Univ. Suita‐shi Jpn

• Kurokawa Atsushi

  Sanyo Electric Co. Ltd

• Hashimoto Masanori

  Osaka Univ.

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