AS-2-2 An Algorithmic Stage Based on the Novel Capacitor Mismatch Calibration Technique
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概要
- 論文の詳細を見る
This paper proposes an algorithmic stage based on the novel capacitor mismatch calibration technique. The conventional stage is improved to this algorithmic circuit involving charge summing, capacitors' exchange and charge redistribution, simply through introducing some extra switches into the analog circuit. Employing this algorithmic stage, one 12-bit pipelined ADC obtains the linearity beyond the accuracy of the capacitor match and verifies the validity of reducing the nonlinear error from the capacitor mismatch without additional power dissipation and chip size through the novel capacitor mismatch calibration technique. It is processed in 0.5um CMOS technology. Simulation results show that 72.6dB SNDR, 78.5dB SFDR are obtained for a 2V Vpp 159.144kHz sine input sampled at 3.7MS/s. The whole power dissipation of the 12-bit ADC is 33.4mW at the power supply of 5V.
- 社団法人電子情報通信学会の論文
- 2008-03-05
著者
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Inoue Yasuaki
Graduate School Of Information Production And Systems Waseda University
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Inoue Yasuaki
Graduate School Of Ips Waseda University
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WANG Shuaiqi
Graduate School of Information, Production and Systems, Waseda University
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LI Fule
Tsinghua University
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Li Fule
Institute of Microelectronics Tsinghua University
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Wang Shuaiqi
Graduate School Of Information Production And Systems Waseda University
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