Impact of Well Edge Proximity Effect on Timing
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概要
- 論文の詳細を見る
This paper studies impact of well edge proximity effect on circuit delay, based on model parameters extracted from test structures in an industrial 65nm wafer process. Experimental results show that up to 10% of delay increase arises by the well edge proximity effect in the 65nm technology, and it depends on interconnect length. Furthermore, due to asymmetric increase in pMOS and nMOS threshold voltages, delay may decrease in spite of the threshold voltage increase. From these results, we conclude that considering WPE is indispensable to cell characterization in the 65nm technology.
- （社）電子情報通信学会の論文
- 2008-12-01
著者
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HASHIMOTO Masanori
Osaka University
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WATANABE Tetsuya
Renesas Technology Corp
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Hashimoto Masanori
Osaka Univ. Suita‐shi Jpn
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Kanamoto Toshiki
Renesas Technology Corp.
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Kanamoto Toshiki
Renesas Design Corp.
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Amishiro Hiroyuki
Renesas Technology Corp.
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OGASAHARA Yasuhiro
Osaka University
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NATSUME Keiko
Renesas Technology Corp.
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YAMAGUCHI Kenji
Renesas Technology Corp.
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Watanabe Tetsuya
Renesas Technology Corp.
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Ogasahara Yasuhiro
Osaka Univ. Suita‐shi Jpn
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Hashimoto Masanori
Osaka Univ.
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