Gate Delay Estimation in STA under Dynamic Power Supply Noise
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概要
- 論文の詳細を見る
This paper presents a gate delay estimation method that takes into account dynamic power supply noise. We review STA based on static IR-drop analysis and a conventional method for dynamic noise waveform, and reveal their limitations and problems that originate from circuit structures and higher delay sensitivity to voltage in advanced technologies. We then propose a gate delay computation that overcomes the problems with iterative computations and consideration of input voltage drop. Evaluation results with various circuits and noise injection timings show that the proposed method estimates path delay fluctuation well within 1% error on average.
- （社）電子情報通信学会の論文
- 2010-12-01
著者
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OKUMURA Takaaki
Semiconductor Technology Academic Research Center
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Hashimoto Masanori
Osaka Univ. Suita‐shi Jpn
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Shimazaki Kenji
Semiconductor Technology Academic Research Center
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MINAMI Fumihiro
Semiconductor Technology Academic Research Center
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KUWADA Kimihiko
Semiconductor Technology Academic Research Center
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Minami Fumihiro
Semiconductor Da Amp Test Engineering Center Toshiba Corporation
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Hashimoto Masanori
Osaka Univ.
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Okumura Takaaki
Semiconductor Technol. Academic Res. Center
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