Gate Delay Estimation in STA under Dynamic Power Supply Noise

スポンサーリンク

概要

• 論文の詳細を見る

• This paper presents a gate delay estimation method that takes into account dynamic power supply noise. We review STA based on static IR-drop analysis and a conventional method for dynamic noise waveform, and reveal their limitations and problems that originate from circuit structures and higher delay sensitivity to voltage in advanced technologies. We then propose a gate delay computation that overcomes the problems with iterative computations and consideration of input voltage drop. Evaluation results with various circuits and noise injection timings show that the proposed method estimates path delay fluctuation well within 1% error on average.

• （社）電子情報通信学会の論文
• 2010-12-01

著者

• OKUMURA Takaaki

  Semiconductor Technology Academic Research Center

• Hashimoto Masanori

  Osaka Univ. Suita‐shi Jpn

• Shimazaki Kenji

  Semiconductor Technology Academic Research Center

• MINAMI Fumihiro

  Semiconductor Technology Academic Research Center

• KUWADA Kimihiko

  Semiconductor Technology Academic Research Center

• Minami Fumihiro

  Semiconductor Da Amp Test Engineering Center Toshiba Corporation

• Hashimoto Masanori

  Osaka Univ.

• Okumura Takaaki

  Semiconductor Technol. Academic Res. Center

関連論文

• Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design(Interconnect,VLSI Design and CAD Algorithms)
• Timing Analysis Considering Spatial Power/Ground Level Variation(Physical Design,VLSI Design and CAD Algorithms)
• Timing Analysis Considering Temporal Supply Voltage Fluctuation
• Successive Pad Assignment for Minimizing Supply Voltage Drop(Power/Ground Network, VLSI Design and CAD Algorithms)
• Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance(Interconnect, VLSI Design and CAD Algorithms)
• Transistor Sizing of LCD Driver Circuit for Technology Migration(Circuit Synthesis,VLSI Design and CAD Algorithms)
• A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays(Circuit Synthesis,VLSI Design and CAD Algorithms)
• Statistical Analysis of Clock Skew Variation in H-Tree Structure(Prediction and Analysis, VLSI Design and CAD Algorithms)
• Impact of Self-Heating in Wire Interconnection on Timing
• An Approach for Reducing Leakage Current Variation due to Manufacturing Variability
• Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations
• Proposal of Metrics for SSTA Accuracy Evaluation(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
• A Method to Derive SSO Design Rule Considering Jitter Constraint(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
• Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation(Interconnect,VLSI Design and CAD Algorithms)
• Gate Delay Estimation in STA under Dynamic Power Supply Noise
• Impact of Well Edge Proximity Effect on Timing
• Delay and Skew Minimized Clock Tree Synthesis for Embedded Arrays (Special Issue on Synthesis and Verification of Hardware Design)
• Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise

もっと見る 閉じる

スポンサーリンク