KASEBE Akira | Meitec Corp.

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著作論文

Determination of Interconnect Structural Parameters for Best-and Worst-Case Delays(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance(Interconnect, VLSI Design and CAD Algorithms)
Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills(Interconnect, VLSI Design and CAD Algorithms)
A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills(VLSI Design Technology and CAD)

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