Masuda Hiroo | Renesas Technology Corp.

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概要

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著作論文

Determination of Interconnect Structural Parameters for Best-and Worst-Case Delays(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance(Interconnect, VLSI Design and CAD Algorithms)
Delay Library Generation with High Efficiency and Accuracy on the Basis of RSM (Special lssue on SISPAD'99)
A New Hierarchical RSM for TCAD-Based Device Design in 0.4μm CMOS Development (Special Issue on Microelectronic Test Structure)
Impact of Self-Heating in Wire Interconnection on Timing
An Approach for Reducing Leakage Current Variation due to Manufacturing Variability
Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations
Proposal of Metrics for SSTA Accuracy Evaluation(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature(Simulation and Verification,VLSI Design and CAD Algorithms)
On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design(Prediction and Analysis, VLSI Design and CAD Algorithms)
Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances(Parasitics and Noise)(VLSI Design and CAD Algorithms)
Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances
Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects
Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation(Interconnect,VLSI Design and CAD Algorithms)
Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills(Interconnect, VLSI Design and CAD Algorithms)
A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills(VLSI Design Technology and CAD)
Modeling and Simulation on Degradation of Submicron NMOSFET Current Drive due to Velocity-Saturation Effects (Special Issue on 1993 VLSI Process and Device Modeling Workshop (VPAD93))
Evaluation of Two-Dimensional Transient Enhanced Diffusion of Phosphorus during Shallow Junction Formation (Special Issue on 1993 VLSI Process and Device Modeling Workshop (VPAD93))
Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis

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