Kobayashi Hiroyuki | Nihon Synopsys Co. Ltd.
スポンサーリンク
概要
関連著者
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KOBAYASHI Hiroyuki
Nihon Synopsys Co., Ltd.
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Kobayashi Hiroyuki
Nihon Synopsys Co. Ltd.
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HASHIMOTO Masanori
Osaka University
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SATO Takashi
Kyoto University
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Sakata Tsuyoshi
Fujitsu Microelectronics Ltd.
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Sato T
Photonic Lattice Inc.:niche Tohoku University
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Masuda Hiroo
Renesas Technology Corp.
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OKUMURA Takaaki
Fujitsu VLSI Ltd.
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HACHIYA Koutaro
NEC Electronics Corp.
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Hachiya Kotaro
Jedat Inc.
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Hashimoto Masanori
Osaka Univ. Suita‐shi Jpn
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Sato Takashi
Institute Of Physics And Tsukuba Research Center For Interdisciplinary Materials Science University
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Hashimoto Masanori
Osaka Univ.
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Okumura Takaaki
Semiconductor Technol. Academic Res. Center
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KANAMOTO Toshiki
Renesas Technology Corporation
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Oka Hiroki
Ntt Advanced Technology Corporation:(present Office)nippon Telegraph And Telephone Corporation
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SATO Takashi
Tokyo Institute of Technology
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KUROKAWA Atsushi
STARC
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NAKASHIMA Hidenari
NEC Electronics Corp.
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ONO Nobuto
Jedat Inc.
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IWAI Jiro
Mathematical Systems Inc.
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SATO Takashi
Renesas Technology Corporation
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AKUTSU Shigekiyo
Oki Electric Industry Co., Ltd.
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NAKABAYASHI Tamiyo
SHARP Corporation
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ICHINOMIYA Takahiro
Matsushita Electric Industrial Co., Ltd.
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ISHIKAWA Hiroshi
Sequence Design, Inc.
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MUROMOTO Sakae
Cadence Design Systems
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Kurokawa Atsushi
Sanyo Electric Co. Ltd.
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Akutsu Shigekiyo
Oki Electric Industry Co. Ltd.
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Kanamoto Toshiki
Mirai‐selete Sagamihara‐shi Jpn
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Kanamoto Toshiki
Renesas Technology Corp.
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Kanamoto Toshiki
Renesas Design Corp.
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Nakashima Hidenari
Integrated Research Institute Tokyo Institute Of Technology
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Ichinomiya Takahiro
Matsushita Electric Industrial Co. Ltd.
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Kurokawa Atsushi
Sanyo Electric Co. Ltd
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Ishikawa Hiroshi
Sequence Design Inc.
著作論文
- Proposal of Metrics for SSTA Accuracy Evaluation(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- A Method to Derive SSO Design Rule Considering Jitter Constraint(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation(Interconnect,VLSI Design and CAD Algorithms)