Nakashima Hidenari | Integrated Research Institute Tokyo Institute Of Technology

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概要

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著作論文

Impact of Self-Heating in Wire Interconnection on Timing
An Approach for Reducing Leakage Current Variation due to Manufacturing Variability
Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations
Proposal of Metrics for SSTA Accuracy Evaluation(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
Wire Length Distribution Model for System LSI(Interconnect, VLSI Design and CAD Algorithms)
Evaluation of X Architecture Using Interconnect Length Distribution(Interconnect, VLSI Design and CAD Algorithms)
Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model(Prediction and Analysis, VLSI Design and CAD Algorithms)
Optimization Technique of Number of Interconnect Layers and Circuit Area Based on Wire Length Distribution

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