INOUE Junpei | Integrated Research Institute Laboratory, Tokyo Institute of Technology

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概要

• 同名の論文著者
• Integrated Research Institute Laboratory, Tokyo Institute of Technologyの論文著者

関連著者

• Masu Kazuya

  Integrated Research Institute

• Okada Kenichi

  Integrated Research Institute Tokyo Institute Of Technology

• INOUE Junpei

  Integrated Research Institute Laboratory, Tokyo Institute of Technology

• NAKASHIMA Hidenari

  Integrated Research Institute Laboratory, Tokyo Institute of Technology

• NAKASHIMA Hidenari

  NEC Electronics Corp.

• Inoue Junpei

  Integrated Research Institute Tokyo Institute Of Technology

• Nakashima Hidenari

  Integrated Research Institute Tokyo Institute Of Technology

• Masu Kazuya

  Solutions Research Laboratory Tokyo Institute Of Technology

• Okada Kenichi

  Tokyo Inst. Of Technol. Yokohama‐shi Jpn

• Uezono Takumi

  Integrated Research Institute Tokyo Institute Of Technology

• Kyogoku Takanori

  Integrated Research Institute Laboratory Tokyo Institute Of Technology

• UEZONO Takumi

  Integrated Research Institute, Tokyo Institute of Technology

• KYOGOKU Takanori

  Integrated Research Institute Laboratory, Tokyo Institute of Technology

• TAKAGI Naohiro

  Integrated Research Institute, Tokyo Institute of Technology

• Takagi Naohiro

  Integrated Research Institute Tokyo Institute Of Technology

• Kyogoku Takanori

  Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan

• Inoue Junpei

  Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan

• Uezono Takumi

  Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan

• Nakashima Hidenari

  Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan

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著作論文

• Wire Length Distribution Model for System LSI(Interconnect, VLSI Design and CAD Algorithms)
• Evaluation of X Architecture Using Interconnect Length Distribution(Interconnect, VLSI Design and CAD Algorithms)
• Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model(Prediction and Analysis, VLSI Design and CAD Algorithms)
• Optimization Methodology of Layer Numbers with Circuit/Process Co-Design

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