Design Guidelines and Process Quality Improvement for Treatment of Device Variations in an LSI Chip(<Special Section>Microelectronic Test Structures)
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概要
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We propose guidelines for LSI-chip design, taking the within-die variations into consideration, and for process quality improvement to suppress the variations. The auto-correlation length, λ, of device variation is shown to be a useful measure to treat the systematic variations in a chip. We may neglect the systematic variation in chips within the range of λ, while σ^2 of the systematic variation must be added to σ^2 of the random variation outside the λ. The random variations, on the other hand, exhibit complete randomness even in the closest pair transistors. The mismatch variations in transistor pairs were enhanced by 1.41(=√<2>) compared with the random variations in single transistors. This requires careful choice of gate size in designing a transistor pair with a minimum size, such as transfer gates in an SRAM cell. Poly-Si gate formation is estimated to be the most important process to ensure the spatial uniformity in transistor current and to enhance circuit performance. Large relative variations are observed for the contact to p^+ diffusion, vial (M1-M2), and via2 (M2-M3) among parameter variations in passive elements. The standard deviations for random variations in vial and via2 are noticeably widespread, indicating the importance of the via resistance control in BEOL. The spatial frequency power spectrum for within-die random variations is confirmed experimentally, as uniform ('white') with respect to the spatial frequency. To treat the large 'white random noise, ' the least-square method with a 4th-order polynomial exhibits a best efficiency as a fitting function for decomposing the raw variation data into systematic part and random part.
- 社団法人電子情報通信学会の論文
- 2005-05-01
著者
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Masuda Hiroo
Semiconductor Technology Academic Research Center (starc)
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Masuda Hiroo
Renesas Technol. Corp. Kodaira‐shi Jpn
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Masuda Hiroo
Semiconductor Technology Academic Research Center
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Aoki Masakazu
Tokyo Univ. Sci. Chino‐shi Jpn
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Aoki Masakazu
Semiconductor and Integrated Circuits Division, Hitachi, Ltd.
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Ohkawa Shin‐ichi
Renesas Technol. Corp. Kodaira‐shi Jpn
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OHKAWA Shinichi
Semiconductor Technology Academic Research Center (STARC)
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Aoki Masakazu
Semiconductor And Integrated Circuits Division Hitachi Ltd.
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