Architecture and Performance Evaluation of a New Functional Memory : Functional Memory for Addition (Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• We propose a functional memory for addition(FMA), which is a memory-merged logic LSI. It is a memory as well as a SIMD parallel processor. To minimize the area, a precessing element(PE) consists of several DRAM words and a bit-serial ALU. The ALU has a functionality of addition bit by bit. This paper describes two FMA experimental LSIs. One is for general purpose, and the other is for full search block matching of image compression. We estimate that a 0.18 μm process realizes 57,000 PEs in a 50 mm^2 die, achieving 205 GOPS under 1.36 W power.

• 社団法人電子情報通信学会の論文
• 2000-12-25

著者

• 小野寺 秀俊

  京都大学工学部電子工学科

• Kobayashi K

  Toyama Prefectural Univ. Toyama‐ken Jpn

• Onodera H

  Kyoto Univ. Kyoto‐shi Jpn

• Onodera Hidetoshi

  Kyoto Univ. Kyoto‐shi Jpn

• 小野寺 秀俊

  滋賀県立大学工学部

• Kobayashi Kazutoshi

  Graduate School Of Informatics Kyoto University

• Onodera Hidetoshi

  Graduate School Of Informatics Kyoto University

• Kobayashi Kensuke

  The Author Is With Lecroy Corp.

• 小野寺 秀俊

  京都大学大学院工学研究科電子通信工学専攻

• YAMAOKA Masanao

  Graduate School of Informatics, Kyoto University

• KOBAYASHI Yukifumi

  Graduate School of Informatics, Kyoto University

• TAMARU Keikichi

  Okayama University of Science

• Kobayashi K

  The Author Is With Lecroy Corp.

• Tamaru K

  Okayama University Of Science

• Yamaoka Masanao

  Graduate School Of Informatics Kyoto University:(present Address) Hitachi Co. Ltd.

• Kobayashi Y

  Graduate School Of Informatics Kyoto University:(present Address) Hitachi Co. Ltd.

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