Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures

スポンサーリンク

概要

• 論文の詳細を見る
• 2011-12-01

著者

• 小野寺 秀俊

  京都大学工学部電子工学科

• Onodera H

  Kyoto Univ. Kyoto‐shi Jpn

• Onodera Hidetoshi

  Kyoto Univ. Kyoto‐shi Jpn

• Kobayashi Kazutoshi

  Graduate School Of Informatics Kyoto University

• Kobayashi Kazutoshi

  Kyoto Univ. Kyoto‐shi Jpn

• Katsuki Kazuya

  Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Universit

• Onodera Hidetoshi

  Graduate School Of Informatics Kyoto University

• 小野寺 秀俊

  京都大学大学院工学研究科電子通信工学専攻

• Furuta Jun

  Department Of Communications And Computer Engineering Kyoto University

• Yamamoto Ryosuke

  Graduate School Of Science And Technology Kobe University

• 小野寺 秀俊

  京都大学情報学研究科通信情報システム専攻:京都大学光・電子理工学教育研究センター

• HAMANAKA Chikara

  Graduate School of Science and Technology, Kyoto Institute of Technology

• FURUTA Jun

  Graduate School of Informatics, Kyoto University

• KUBOTA Kanto

  Graduate School of Science and Technology, Kyoto Institute of Technology

• Kubota Kanto

  Graduate School Of Science And Technology Kyoto Institute Of Technology

• Hamanaka Chikara

  Graduate School Of Science And Technology Kyoto Institute Of Technology

• Furuta Jun

  Graduate School Of Informatics Kyoto University

関連論文

• Spreading Code Assignment for Multicarrier CDMA System over Frequency-Selective Fading Channels(Terrestrial Radio Communications)
• パネル討論 : 設計/CAD技術はディープサブミクロン時代の挑戦に耐えられるか
• Inter-Code Interference and Optimum Spreading Sequence in Frequency-Selective Rayleigh Fading Channels on Uplink MC-CDMA(Signal Processing for Communications)(Digital Signal Processing)
• CMOS論理ゲートにおける貫通電流による消費電力の定式化
• 抵抗アレイモデルを用いたアナログ回路用概略配線
• 形状最適化コンパクション
• ビルディングブロックレイアウトのための分枝限定配置手法
• ばらつき考慮設計に向けて(アナログ,アナデジ混載,RF及びセンサインタフェース回路)
• ばらつき考慮設計に向けて(アナログ,アナデジ混載,RF及びセンサインタフェース回路)
• 基板バイポーラ効果によるSEUとMCUの発生機構の検討(製造性考慮設計,システムオンシリコンを支える設計技術)
• C-12-56 ω_nドメイン設計手法によるCDR-ICの低ジッタ化(C-12.集積回路,一般セッション)
• Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling(Analog Circuits and Related SoC Integration Technologies)
• Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line(Interconnect,VLSI Design and CAD Algorithms)
• Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design(Interconnect,VLSI Design and CAD Algorithms)
• Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
• Representative Frequency for Interconnect R(f)L(f)C Extraction(Parasitics and Noise)(VLSI Design and CAD Algorithms)
• Instruction-Level Power Estimation Method by Considering Hamming Distance of Registers(Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
• PA-1 大学の研究をどのように産業界に活かすか?
• モデル依存性の小さいMOSFETパラメータ抽出システムの実現
• AI-1-3 ディペンダブルVLSIプラットフォームへの挑戦(AI-1.デイベンダブルVLSIに向けて,依頼シンポジウム,ソサイエティ企画)
• A 90nm 48×48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations(Low-Power and High-Performance VLSI Circuit Technology,VLSI Technology toward Frontiers of New Market)
• A 90nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations(Digital,Low-Power, High-Speed LSIs and Related Technologies)
• A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era(Digital, Low-Power LSI and Low-Power IP)
• Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver(Analog Circuits and Related SoC Integration Technologies)
• A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era(Electronic Circuits)
• D-10-5 An Instruction Decomposition Scheme to Aid Fine-Grained Online Recovery in Pipeline Processor
• Experimental Study on Cell-Base High-Performance Datapath Design(IP Design)(VLSI Design and CAD Algorithms)
• Experimental Study on Cell-Base High-Performance Datapath Design
• Timing Analysis Considering Spatial Power/Ground Level Variation(Physical Design,VLSI Design and CAD Algorithms)
• 不確定パラメタの導入によるアナログ回路設計手順の再利用率向上手法
• A-58 モデル依存性の小さいMOSFETパラメータ抽出システムの実現(A-3. VLSI設計技術,一般講演)
• モデル依存性の小さいMOSFETパラメータ抽出手法
• アナログ回路設計手順の保存・再利用化手法
• C-12-60 Accurate Individual Gate Delay Measurement to Study Within-die Variations
• Special Section on Analog Circuit Techniques for System-on-Chip Integration
• FOREWORD (Special Section on Analog Technologies in Submicron Era)
• Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration
• デザインルールチェック並列処理化の一手法 : 並列スケジューリングによる手順割り当て
• デザインルールチェック並列処理化の一手法 : 並列スケジューリングによる手順割り当て
• 中間モデルを用いたモデル依存性の小さいMOSFETパラメータ抽出手法
• Timing Analysis Considering Temporal Supply Voltage Fluctuation
• Successive Pad Assignment for Minimizing Supply Voltage Drop(Power/Ground Network, VLSI Design and CAD Algorithms)
• An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity
• Score-Level Fusion of Phase-Based and Feature-Based Fingerprint Matching Algorithms
• A Robust 3D Face Recognition Algorithm Using Passive Stereo Vision
• 特集「システムLSI設計とその技術」の編集にあたって
• アナログ/ディジタル混載LSIのCAD技術
• BPBP型FMPPを用いたプロセッサボードの設計
• Model-Adaptable Parameter Extraction System for MOSFET Models
• Development of Module Generators from Extracted Design Procedures : Application to Analog Device Generation
• A-3-13 SystemC を用いたハードウェア・ソフトウェア設計 : SystemC のRTL記述からHDLへの変換
• A-3-12 SystemC を用いたハードウェア・ソフトウェア強調設計
• Architecture and Performance Evaluation of a New Functional Memory : Functional Memory for Addition (Special Section on VLSI Design and CAD Algorithms)
• A Real-Time Low-Rate Video Compression Algorithm Using Multi-Stage Hierarchical Vector Quantization (Special Section on VLSI for Digital Signal Processing)
• An LSI for Low Bit-Rate Image Compression Using Vector Quantization(Special Issue on Multimedia, Network, and DRAM LSIs)
• A Memory-Based Parallel Processor for Vector Quantization:FMPP-VQ (Special Issue on New Concept Device and Novel Architecture LSIs)
• A Current Mode Cyclic A/D Converter with Submicron Processes (Special Section on Analog Circuit Techniques for System-on-Chip Integration)
• A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture (Special Issue on New Architecture LSIs)
• High-Accuracy Estimation of Image Rotation Using 1D Phase-Only Correlation
• A Passive 3D Face Recognition System and Its Performance Evaluation
• A Palmprint Recognition Algorithm Using Phase-Only Correlation
• A Fingerprint Matching Algorithm Using Phase-Only Correlation(Digital Signal Processing for Pattern Recognition)(Applications and Implementations of Digital Signal Processing)
• An Auction Protocol Preserving Privacy of Losing Bids with a Secure Value Comparison Scheme (Applications) (Cryptography and Information Security)
• B-5-83 Evaluation of Inter-code Interference on Uplink MC-CDMA
• High-Accuracy Subpixel Image Registration Based on Phase-Only Correlation(Digital Signal Processing)
• Fibered 2-bridge link and Conway notation
• An Efficient Motion Estimation Algorithm Using a Gyro Sensor(Video/Image Coding)(Applications and Implementations of Digital Signal Processing)
• A Comprehensive Simulation and Test Environment for Prototype VLSI Verification(Verification)(Test and Verification of VLSI)
• FOREWORD (Special Issue on Synthesis and Verification of Hardware Design)
• Micro-Loading効果を考慮したCMOS回路の比精度解析
• レイアウトを考慮したCMOS回路の比精度解析
• Development of procedure for modeling MOSFET compatible with ITRS: noise and 1-5 characteristics modeling for RF/analog MOSFET (集積回路)
• More Mooreに立ちはだかるCMOSばらつきの理解に向けて(低電力設計,システムオンシリコンを支える設計技術)
• ビット並列ブロック並列型FMPPにおける機能メモリのテスト方法
• ビット並列ブロック並列型FMPPアーキテクチャをとるプロトタイプLSIチップの概要
• ビット並列ブロック並列方式による機能メモリ型並列プロセッサの設計
• C-12-46 完全差動回路構成GVCOの高速化設計(C-12.集積回路,一般セッション)
• C-12-25 On-chip Monitor Circuits to Estimate Global Variations of Threshold Voltage and Gate Length
• Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System
• Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures
• Higher-Order Effect of Source--Drain Series Resistance on Saturation Drain Current in Sub-20 nm Metal--Oxide--Semiconductor Field-Effect Transistors
• NBTI-Induced Delay Degradation Analysis of FPGA Routing Structures
• A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect

もっと見る 閉じる

スポンサーリンク