Experimental Study on Cell-Base High-Performance Datapath Design(IP Design)(<Special Section>VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
This paper experimentally investigates the effectiveness of regularly-placed bit-slice layout and transistor-level optimization to datapath circuit performance. We focus on cell-base design flows with transistor-level circuit optimization. We examine the effectiveness through design experiments of 32-bit carry select adder and 16-bit tree-style multiplier in a 0.35 μm technology. From the experimental results, we can scarcely observe that manual cell placement contributes to improve circuit performance. On the other hand, transistor-level circuit optimization is so effective that circuit delay is reduced by 11-20% and power dissipation decreases to 42-62%. We can see that, in the case of cell-base design, transistor-level optimization is also important as well as in the case of custom design, whereas cell-base bit-slice layout has less importance to circuit performance.
- 社団法人電子情報通信学会の論文
- 2003-12-01
著者
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小野寺 秀俊
京都大学工学部電子工学科
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Onodera Hidetoshi
Department of Communications and Computer Engineering, Kyoto University
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Onodera H
Kyoto Univ. Kyoto‐shi Jpn
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Onodera Hidetoshi
Kyoto Univ. Kyoto‐shi Jpn
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Onodera Hidetoshi
Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Universit
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HASHIMOTO Masanori
Department of Information Systems Engineering, Osaka University
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小野寺 秀俊
滋賀県立大学工学部
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HAYASHI Yoshiteru
Department of Communications and Computer Engineering, Kyoto University
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小野寺 秀俊
京都大学大学院工学研究科電子通信工学専攻
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Hayashi Yoshiteru
Department Of Communications And Computer Engineering Kyoto University
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Hashimoto M
Kyoto Univ. Kyoto‐shi Jpn
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Hashimoto Masanori
Department Of Communications And Computer Engineering Kyoto University
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Hashimoto Masanori
Department Of Breast And Endocrine Surgery University Of Tokyo
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Onodera Hidetoshi
Department of Communication and Computer Engineering, Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan
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