Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution
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概要
- 論文の詳細を見る
Influence of manufacturing variability on circuit performance has been increasing because of finer manufacturing process and lowered supply voltage. In this paper, we focus on mesh-style clock distribution which is believed to be effective for reducing clock skew, and we evaluate clock skew considering manufacturing and design variabilities. Considering MOS transistor variation — random and spatially-correlated variation — and non-uniform flip-flop (FF) placement, we demonstrate that spatially-correlated variation and severe non-uniform FF distribution can be major sources of clock skew. We also examine the dependency of clock skew on design parameters, and reveal that finer clock mesh does not necessarily reduce clock skew.
- （社）電子情報通信学会の論文
- 2008-12-01
著者
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ABE Shinya
Department of Radiopharmacy, Tohoku Pharmaceutical University
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HASHIMOTO Masanori
Department of Information Systems Engineering, Osaka University
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Onoye Takao
Department Of Information Systems Engineering Osaka University
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Onoye Takao
Department Of Communications And Computer Engineering Kyoto University
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Hashimoto Masanori
Department Of Communications And Computer Engineering Kyoto University
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Abe Shinya
Department Of Information Systems Engineering Osaka University
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Abe Shinya
Department Of Cardiology Tobu Chiiki Hospital Tokyo Metropolitan Health And Medical Treatment Corpor
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Hashimoto Masanori
Department Of Breast And Endocrine Surgery University Of Tokyo
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