Low-Power VLSI Implementation by NMOS 4-Phase Dynamic Logic (特集電子システムの設計技術と設計自動化)

概要

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An nMOS 4-phase dynamic logic scheme is described, which is intended mainly to achieve low-power consumption. In this scheme, the short-circuit current of a logic gate is eliminated, and moreover, the capacitive load of the gate is reduced to almost half as compared with the corresponding CMOS gate, resulting in enhancing the power reduction and shortening the gate delay. A new layout concept of Array Cell (AC) is introduced, which contains (M×N)+2 transistors to construct a logic gate, and is used for the basic logic component in the nMOS 4-phase dynamic logic scheme. The regular structure of the AC contributes much toward the reduction of total layout area. Moreover, a clock generator dedicated to generating four types of clock signals is devised for reducing the complexity of clock distribution. A number of experimental results of logic modules are also shown to demonstrate that not only the low-power dissipation but also the high density can be attained.
一般社団法人情報処理学会の論文
2000-04-15