Estimation of Short-Circuit Power Dissipation for Static CMOS Gates (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)

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概要

• 論文の詳細を見る

• We present a formula of short-circuit power dissipation for static CMOS logic gates. By representing short-circuit current by a piece-wise linear function and considering a current flowing from input node to output node through gate capacitances, the accuracy is improved significantly. The error of our formula in a CMOS inverter is less than 15% from circuit simulation in many cases of our experiments. A improved circuit simulation technique for short-circuit power dissipation is presented. Since this formula calculate the short-circuit power dissipation accurately and quickly, it will be applied to power sensible CAD tools.

• 社団法人電子情報通信学会の論文
• 1996-03-25

著者

• Hirata Akio

  Faculty Of Engineering Kyoto Sangyo University

• Hirata Akio

  Faculty Of Engineering Kyoto University

• Onodera Hidetoshi

  Faculty of Engineering, Kyoto University

• Tamaru Keikichi

  Faculty of Engineering, Kyoto University

• Onodera Hidetoshi

  Faculty Of Engineering Kyoto University

• Tamaru Keikichi

  Faculty Of Elctronics Kyoto University

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